| 快讯名称 |
内容类型 |
文件类型 |
|
AD9540: 655 MHz Low Jitter Clock Generator Data Sheet (Rev A, 02/2006) (pdf, 839 kB)
|
产品数据手册 |
PDF
|
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AN-953: 具可编程模数的直接数字频率合成器(DDS)
(pdf, 99 kB)
|
应用笔记 |
PDF
|
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AN-953: Direct Digital Synthesis (DDS) with a Programmable Modulus
(pdf, 112 kB)
|
应用笔记 |
PDF
|
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AN-939: 利用AD9912的超奈奎斯特频率操作得到高RF输出信号
(pdf, 0)
|
应用笔记 |
PDF
|
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AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal
(pdf, 221 kB)
|
应用笔记 |
PDF
|
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AN-927: 确定杂散来源是DDS/DAC还是其他器件(例如开关电源)[中文版]
(pdf, 234 kB)
|
应用笔记 |
PDF
|
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AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies)
(pdf, 170 kB)
|
应用笔记 |
PDF
|
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AN-873: ADF4xxx系列PLL频率合成器的锁定检测
(pdf, 0)
|
应用笔记 |
PDF
|
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AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers
(pdf, 207 kB)
|
应用笔记 |
PDF
|
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AN-851: 一种WiMax双下变频IF采样接收机设计方案[中文版]
(pdf, 421 kB)
|
应用笔记 |
PDF
|
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AN-851: A WiMax Double Downconversion IF Sampling Receiver Design
(pdf, 262 kB)
|
应用笔记 |
PDF
|
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AN-847: 用AD5933测量接地阻抗特性
(pdf, 294 kB)
|
应用笔记 |
PDF
|
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AN-847: Measuring a Grounded Impedance Profile Using the AD5933
(pdf, 294 kB)
|
应用笔记 |
PDF
|
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AN-843: 用AD5933测量扬声器阻抗特性
(pdf, 513 kB)
|
应用笔记 |
PDF
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AN-843: Measuring a Loudspeaker Impedance Profile Using the AD5933 (Rev. A, 6/07)
(pdf, 284 kB)
|
应用笔记 |
PDF
|
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AN-837: 基于DDS的时钟抖动性能与DAC重构滤波器性能的关系[中文版]
(pdf, 416 kB)
|
应用笔记 |
PDF
|
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AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance
(pdf, 313 kB)
|
应用笔记 |
PDF
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AN-823: 时钟应用中的直接数字频率合成器[中文版]
(pdf, 303 kB)
基于直接数字频率合成器的时钟系统的时间抖动
|
应用笔记 |
PDF
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AN-823: Direct Digital Synthesizers in Clocking Applications Time
(pdf, 115 kB)
Jitter in Direct Digital Synthesizer-Based Clocking Systems
|
应用笔记 |
PDF
|
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AN-772: 引脚架构芯片级封装（LFCSP）设计与制造指南
(pdf, 828 kB)
|
应用笔记 |
PDF
|
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AN-772: A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP)
(pdf, 439 kB)
|
应用笔记 |
PDF
|
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AN-769: 基于AD9540产生多时钟输出
(pdf, 130 kB)
|
应用笔记 |
PDF
|
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AN-769: Generating Multiple Clock Outputs from the AD9540
(pdf, 0)
|
应用笔记 |
PDF
|
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AN-756: 系统采样以及时钟相位噪声和抖动的影响[中文版]
(pdf, 808 kB)
|
应用笔记 |
PDF
|
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AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter
(pdf, 291 kB)
|
应用笔记 |
PDF
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AN-741: 鲜为人知的相位噪声特性
(pdf, 359 kB)
|
应用笔记 |
PDF
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AN-632: 利用AD9951 DDS作为ADN2812连续速率CDR的捷变参考时钟以提供数据速率
(pdf, 298 kB)
|
应用笔记 |
PDF
|
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AN-632: Provisionary Data Rates Using the AD9951 DDS as an Agile Reference Clock for the ADN2812 Continuous-Rate CDR
(pdf, 138 kB)
|
应用笔记 |
PDF
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AN-621: AD9832/AD9835的编程
(pdf, 171 kB)
本应用笔记将详细描述如何将AD9832/AD9835器件的输出编程为5 MHz。其中将详细说明频率寄存器(frequency register)、迟延寄存器(defer register)和命令序列(command sequence)。
|
应用笔记 |
PDF
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AN-621: Programming the AD9832/AD9835
(pdf, 202 kB)
This application note details how to program 5 MHz on the output of the AD9832/AD9835 parts. The frequency
register,defer register,and command sequence are explained in detail.
|
应用笔记 |
PDF
|
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AN-605: 同步多个基于DDS的频率合成器AD9852
(pdf, 0)
|
应用笔记 |
PDF
|
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AN-605: Synchronizing Multiple AD9852 DDS-Based Synthesizers
(pdf, 527 kB)
|
应用笔记 |
PDF
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AN-587: 同步多个基于DDS的频率合成器AD9850/AD9851
(pdf, 724 kB)
|
应用笔记 |
PDF
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AN-587: Synchronizing Multiple AD9850/AD9851 DDS-Based Synthesizers
(pdf, 116 kB)
|
应用笔记 |
PDF
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AN-557: 实验者项目：
(pdf, 942 kB)
在业余无线电收发器内集成AD9850 DDS器件以实现数字本振功能*
|
应用笔记 |
PDF
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AN-557: An Experimenter's Project:
(pdf, 368 kB)
Incorporating the AD9850 Complete DDS Device as a Digital LO Function in an Amateur Radio Transceiver
|
应用笔记 |
PDF
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AN-543: 利用ADSP-2181 DSP和AD9850直接数字频率合成器产生高质量、全数字RF频率调制
(pdf, 335 kB)
|
应用笔记 |
PDF
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AN-543: High Quality, All-Digital RF Frequency Modulation Generation with the ADSP-2181 and the AD9850 DDS
(pdf, 49 kB)
|
应用笔记 |
PDF
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AN-501: 孔径不确定度与ADC系统性能[中文版]
(pdf, 227 kB)
在中频采样中的一个关键问题是孔径不确定度（抖动）
|
应用笔记 |
PDF
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AN-501: Aperture Uncertainty and ADC System Performance
(pdf, 227 kB)
A Key Concern in IF Sampling is that of Aperture Uncertainty (Jitter)
|
应用笔记 |
PDF
|
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AN-423: 直接数字频率合成器AD9850的幅度调制
(pdf, 159 kB)
|
应用笔记 |
PDF
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AN-423: Amplitude Modulation of the AD9850 Direct Digital Synthesizer
(pdf, 37 kB)
|
应用笔记 |
PDF
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AN-419: 用于完整的直接数字频率合成器AD9850的分立、低相位噪声、125MH晶振
(pdf, 216 kB)
|
应用笔记 |
PDF
|
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AN-419: A Discrete, Low Phase Noise, 125 MHz Crystal Oscillator for the AD9850
(pdf, 101 kB)
|
应用笔记 |
PDF
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AN-345: 低频和高频电路接地
(pdf, 823 kB)
了解接地路径和信号路径，实现行之有效的设计。电流沿着阻抗最小，而不仅是电阻最小的路径流动……
|
应用笔记 |
PDF
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AN-345: Grounding for Low-and-High-Frequency Circuits
(pdf, 455 kB)
Know Your Ground and Signal Paths for Effective Designs. Current Flow Seeks Path of Least Impedance-Not Just Resistance....
|
应用笔记 |
PDF
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AN-342: 高速、高精度处理模拟信号[中文版]
(pdf, 466 kB)
用于优化DAC和ADC性能的信号处理技术
|
应用笔记 |
PDF
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AN-342: Analog Signal-Handling for High Speed and Accuracy.
(pdf, 468 kB)
Signal handling techniques for optimizing DAC and ADC performance.
|
应用笔记 |
PDF
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AN-280: Mixed Signal Circuit Technologies
(pdf, 2101 kB)
Considers problems which arise when reality (& Murphy) intervene in a design which otherwise seems satisfactory in terms of theory and modeling.
|
应用笔记 |
PDF
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AN-237: 放大器直接数字频率合成的DAC选型器应用漫谈
(pdf, 1156 kB)
|
应用笔记 |
PDF
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AN-237: Choosing DACs for Direct Digital Synthesis
(pdf, 1156 kB)
|
应用笔记 |
PDF
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高性能时钟: 解密抖动
现在每个电子设备一般都有多个时钟，所以必须考虑到这些时钟的抖动性能。低抖动和低相位噪声的时钟对数字信号的处理是非常重要的。所谓时钟抖动是指时钟触发沿的随机误差，通常可以用两个或多个时钟周期之间的差值来量度，这个误差是由时钟发生器内部产生的。时钟的抖动将会影响到仪表的精确测量，在无线通信中将会引起更高的误码率和不良的通信质量，时钟的相位噪声也会引起数据误差和降低数据吞吐量。因此，欢迎大家和我们一起探讨亚皮秒抖动的时钟性能。在这次在线研讨会上，我们将详细探讨抖动和相位噪声的关系以及亚皮秒抖动和超低相位噪声的测量方法。这次在线研讨会还将会涵盖高性能时钟IC的应用考虑。ADI公司的新型ADIsimCLK时钟仿真工具的使用也将会在这次研讨会上作详细介绍。
|
在线研讨会 |
WEBCAST
|
Fundamentals of Frequency Synthesis, Part 2: Direct Digital Synthesis (DDS)
This month we conclude our two-part series on frequency synthesis, with an introduction to Direct Digital Synthesis. We will give a basic review of how a direct digital synthesis system works, touching on the inner workings of the DDS engine at a relatively high level. We will also discuss the tradeoffs between PLL and DDS technology as a base choice for frequency synthesis needs.
|
在线研讨会 |
WEBCAST
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应用工程师问答——33：直接数字频率合成全攻
(模拟对话，第38卷，2004年8月)
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《模拟对话》杂志 |
HTML
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Speedy A/Ds Demand Stable Clocks
by Jeff Keip, Analog Devices, Inc. (EE Times, 3/18/04)
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技术文章 |
HTML
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Design A Clock-Distribution Strategy With Confidence
by Demetrios Efstathiou
(Electronic Design, April 27, 2006)
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技术文章 |
HTML
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Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems
... Much of your system's performance depends on jitter specifications, so careful assessment is critical.
by Brad Brannon, Analog Devices (EDN, 12/7/2004)
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技术文章 |
HTML
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Low-power direct digital synthesizer cores enable high level of integration
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技术文章 |
HTML
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Improved DDS Devices Enable Advanced Comm Systems
by Valoree Young, Analog Devices
(Electronic Products, September 2006)
|
技术文章 |
HTML
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ADI Buys Korean Mobile TV Chip Maker
(EE Times, 6/7/2006)
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技术文章 |
HTML
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DDS Device Provides Amplitude Modulation
by Mary McCarthy, Analog Devices, Inc.
(EDN, September 2, 1999)
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技术文章 |
HTML
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Introducing Digital Up/Down Converters: VersaCOMM™ Reconfigurable Digital Converters
(pdf, 63 kB)
Revolutionize your radio architectures
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技术文章 |
PDF
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Digital Up/Down Converters: VersaCOMM™ White Paper
(pdf, 97 kB)
|
技术文章 |
PDF
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Basics of Designing a Digital Radio Receiver (Radio 101)
(pdf, 77 kB)
|
技术文章 |
PDF
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The Year of the Waveform Generator
(Test & Measurement World, 12/1/2005)
|
技术文章 |
HTML
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Synchronized Synthesizers Aid Multichannel Systems
by David Brandon and John Kornblum, Analog Devices, Inc. (Microwaves & RF, 9/2005)
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技术文章 |
HTML
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DDS Applications
by Eva Murphy and Colm Slattery, Analog Devices, Inc. (EETimes, 9/26/2005)
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技术文章 |
HTML
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DDS IC Initiates Synchronized Signals
(Microwaves & RF Cover Story, July 2005)
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技术文章 |
HTML
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Digital Waveform Generator Provides Flexible Frequency Tuning for Sensor Measurement
by Colm Slattery, Analog Devices (EDN, 12/17/2004)
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技术文章 |
HTML
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DDS Simplifies Polar Modulation
By Ken Gentile, Analog Devices ... Basic modulation mathematics and DDS (direct digital synthesis) provide designers with an all-digital technique for generating polar-encoded carrier signals. (EDN, 8/5/2004)
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技术文章 |
HTML
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DDS Circuit Generates Precise PWM Waveforms
by Colm Slattery, Analog Devices, Inc. (EDN, 10/2/2003)
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技术文章 |
HTML
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DDS IC Plus Frequency-To-Voltage Converter Make Low-Cost DAC
by Noel McNamara, Analog Devices, Inc. (EDN Design Idea, 2/5/2004)
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技术文章 |
HTML
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Simple Circuit Controls Stepper Motors
by Noel McNamara, Analog Devices, Inc. (EDN Design Idea, 1/8/04)
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技术文章 |
HTML
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Integrated DDS Chip Takes Steps To 2.7 GHz
This highly integrated 2.7-GHz source includes all essential DDS circuitry along with a clock driver, divider, high-resolution DAC, and combination phase detector/charge pump. (ED Online, April 2004)
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技术文章 |
HTML
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Two DDS ICs Implement Amplitude-shift Keying
by Noel McNamara, Analog Devices, Inc. (EDN Design Idea, 12/25/2003)
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技术文章 |
HTML
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AD9858: Flexible Integrated Synthesizer For Wireless
(htm)
... The most important feature of the AD9858 is its ability to change frequency in less than 5 ns, meaning that there is virtually no application left where you will need to go the expense of switching between two separate synthesizers. (AnalogZone, RF/IF Zone Products for the Week of 9/23/2002)
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技术文章 |
HTM
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DDS Device Produces Sawtooth Waveform
Ramp or sawtooth waveforms are useful for a broad range of applications, including automatic-test equipment, benchtest equipment, and actuator control. (EDN Design Idea, 7/10/2003)
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技术文章 |
HTML
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400-MSample DDSs Run On Only +1.8 VDC
... This line of highly integrated DDS ICs features on-board RAM and
crystal-oscillator circuitry to simplify the generation of agile and exotic waveforms. (Microwaves & RF Cover Story, 12/2002)
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技术文章 |
HTML
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DDS Tackles BaseStations Head On
... This High-Performance, Low-Power Integrated Hybrid Synthesizer Flaunts A 10-b Digital-To-Analog Converter
That Operates At Up To 1 GSample/s.
(Wireless Systems Design, September 2002)
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技术文章 |
HTML
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Digital Potentiometers Vary Amplitude In DDS Devices
(PDF)
(Electronic Design, Ideas for Design, 5/29/2000)
|
技术文章 |
PDF
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Video Portables and Cameras Get HDMI Outputs
By Doug Bartow, Analog Devices, Inc.
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技术文章 |
HTML
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Clock Requirements For Data Converters
(Electronic Design, 2/2005)
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技术文章 |
HTML
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DDS Design
By David Brandon, Analog Devices, Inc.
Direct digital synthesizers are known for their highly accurate digital tuning, low noise figure, and phase-continuous frequency-hopping capabilities, which make them more attractive than alternative analog frequency-synthesis solutions.
(EDN, 5/13/2004)
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技术文章 |
HTML
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Analog-to-Digital Converter Clock Optimization: A Test Engineering Perspective
(pdf, 909 kB)
By Rob Reeder, Wayne Green, and Robert Shillito
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技术资料 |
PDF
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Free Direct Digital Synthesis IC Evaluation Tool
(Control Engineering, 9/14/2006)
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产品评述 |
HTML
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On-Line Evaluation Tool Simplifies Implementing DDS Semiconductors
(eeProductCenter, 8/16/2006)
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产品评述 |
HTML
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Circuit Simulation Tool Simplifies Clock Designs
(eeProductCenter, 8/23/2005)
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产品评述 |
HTML
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Where Analog Really Meets Digital
(EE Time, 8/29/2005)
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产品评述 |
HTML
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Ultra-low Jitter Performance Marks Analog Devices' Entry into the Clock IC Market
(eeProductCenter, 12/8/04)
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产品评述 |
HTML
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Clock-circuit-design Tool Recovers Engineer Time
(EDN, 8/23/2005)
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产品评述 |
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Low Jitter Clock Generator for Data Converters
... Analog Devices' first dedicated clocking product supporting the stringent needs of high performance data converters. (AVNET Technology Review, November 2004,
Vol. 10, Issue 11)
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产品评述 |
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Expanding Family of Integrated Clock ICs
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概况 |
HTML
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时钟和定时产品
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概况 |
HTML
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Leading Inside Advertorials: Single-Chip Clock Generator with 14-Channel Distribution Solves Timing Challenges in Networks
(pdf, 64 kB)
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概况 |
PDF
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Optical and High Speed Networking
(pdf, 2236 kB)
Analog Devices’ optical and high speed networking ICs solve a depth
and breadth of challenges faced by today’s designers of datacom
and telecom systems, optical modules, and subsystems. Analog
Devices products address a wide range of networking applications
from O/E/O conversion, clock recovery, and backplane transmission
to monitoring and control of optical power, power management, and
clock generation and distribution.
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概况 |
PDF
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Reset your thinking about clocks.
(pdf, 153 kB)
... In precision timing, analog is everywhere.
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概况 |
PDF
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Clock and Timing ICs
(pdf, 4970 kB)
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概况 |
PDF
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My evaluation board is not working; the software is reporting a USB Communication Error. I verified that the evaluation board is connected to the PC and powered. What else can I check?
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常见问题解答 |
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Why do I see reference spurs?
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常见问题解答 |
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Why is my phase noise shape changing when I change the PLL settings?
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常见问题解答 |
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Why doesn't the PLL make my reference input and the clock outputs line up?
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常见问题解答 |
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How do I optimize my PLL loop for the best phase noise and/or jitter?
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常见问题解答 |
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My loop is not locking. How do I debug this?
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常见问题解答 |
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How long does it take for the PLL to lock?
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常见问题解答 |
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Help! My PLL came unlocked over temperature.
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常见问题解答 |
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How do I choose between active and passive filter in PLL loop?
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常见问题解答 |
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Should I reference the passive filter to ground? or supply?
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常见问题解答 |
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How do the PLLs in the AD951x parts compare to other ADI PLLs?
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常见问题解答 |
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How does the clock clean-up function of the AD951x parts work?
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常见问题解答 |
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Why do I want to run a fast PFD frequency?
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常见问题解答 |
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Is it ok for me to connect the same power supply to both the charge pump and distribution power supply pins?
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常见问题解答 |
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Why can't I use a bandpass filter for my loop filter?
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常见问题解答 |
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Should I tie my loop filter to ground or PLL supply?
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常见问题解答 |
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The loop filter was working great until I changed the divide ratio in PLL. What happened?
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常见问题解答 |
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How do I use a VCO with a supply greater than 5V?
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常见问题解答 |
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What suppliers do you recommend for VCO/VCXOs?
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常见问题解答 |
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Do VCXOs have better phase noise and jitter performance than VCOs?
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常见问题解答 |
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How do I know which VCO will work best with the AD9510?
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常见问题解答 |
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Is there an advantage to running a higher VCO frequency than the output frequency?
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常见问题解答 |
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How do I determine if a VCO is good enough for my purpose?
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常见问题解答 |
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Is there any difference between the nature of an oscillator's phase noise and the phase noise from a clock chip?
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常见问题解答 |
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Do different divide ratios cause variations in jitter?
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常见问题解答 |
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I have a clocking scheme which requires several different division ratios simultaneously. I have a frequency plan, but I'm concerned about crosstalk. How much of a problem is this with your clock distribution chips?
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常见问题解答 |
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Do divide ratios change the propagation delay?
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常见问题解答 |
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I want to use the phase offset feature on the AD9510 dividers to generate two signals 90° out of phase. How accurate is the phase offset?
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常见问题解答 |
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On the AD951x clock ICs, does the phase offset (coarse delay) affect the jitter?
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常见问题解答 |
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Why doesn't the mini-divider support the divide ratio I want?
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常见问题解答 |
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I want to use the variable delay adjust, but the jitter is too high. What can I do?
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常见问题解答 |
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I changed the coarse phase adjust in the evaluation software, but nothing happened. What's going on?
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常见问题解答 |
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What is the difference between the coarse phase adjust and the fine delay adjust?
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常见问题解答 |
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What is the fine delay adjust which is available on certain LVDS/CMOS outputs?
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常见问题解答 |
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Does the fine delay adjust affect the jitter?
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常见问题解答 |
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Why is the fine delay adjust not available on all the outputs?
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常见问题解答 |
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Is there a way to cause Input/Output rising edges to be synchronous (zero delay) with the AD9510/11?
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常见问题解答 |
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Will the AD9510 work without a reference input signal?
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常见问题解答 |
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What are the best clock sources for a distribution-only design?
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常见问题解答 |
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I am not using the CLK1 input on the AD9510. Can I just leave it floating?
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How good does my input signal need to be?
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I turned off my reference but the Digital Lock Detect (DLD) still says I'm locked.
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Can I shift the threshold on clocks for single-ended inputs?
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The reference input is differential, but my reference is single-ended. Do I need to convert to differential to drive the AD9510?
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Will differential or single-ended inputs/outputs improve my jitter?
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Why should I use differential rather than single-ended?
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How do I feed a single-ended signal into a differential input?
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Why do you recommend AC coupling, rather than DC coupling, at the clock inputs?
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Are the ADI clock parts stand-alone clock sources or do I still have to buy a clock source to drive these parts?
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Which provides better performance - a clock source with sinewave output, or one with differential square wave outputs?
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On the AD9510, what is the relationship between clock output jitter and CLK1/CLK2 input slew rate?
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I'm trying to write to the part in single-byte mode, but I can't write anything. What am I doing wrong?
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Can I use the 951X clocks to drive a mixer (RF LO)?
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My applications are RF, not for clocking data converters. Can ADI's 951X ICs be used for RF applications?
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I have an input present at the clock input, but I'm not seeing an output?
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What happens to the AD9510/11 clock outputs if the Reference Input (REFIN) signal goes away?
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What clock frequency comes out of the AD9510 outputs when you first apply power to the device?
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Is it possible to impedance match a clock output if it is heavily loaded? (e.g. CL=100pF)
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I ran the AD9510 outputs at 1.4 GHz and they seem to work fine. Is there a problem running them at 1.4 GHz?
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What should I do with unused channels on the AD9510?
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Can I tri-state the AD9510 outputs?
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On the AD9510, how can I make sure that the duty cycle of output clocks stays within 40% to 60% duty cycle window?
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What is the effect of distributing harmonically related clocks (on chip or on board) in terms of jitter?
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Is there any reason to use a transformer on a differential clock output to obtain a "clean" single-ended clock output?
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What are some of the advantages/disadvantages of using LVPECL vs. LVDS outputs?
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Does the AD9510 support 2.5V PECL?
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How much bandwidth is required to process a PECL or LVDS output?
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If I use only one of the PECL differential outputs and the unused output is terminated in 50Ω, how will this affect the phase noise or jitter of the single-ended output?
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If I change the level of PECL output, does it affect the jitter?
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What is the best way to terminate LVPECL outputs to get lowest jitter?
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Is it okay to AC-couple PECL or LVDS outputs?
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What is the fan-out capability of the CMOS, LVDS, and LVPECL outputs?
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What is the proper termination (value and location) for outputs?
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Are outputs short-circuit protected?
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Are the CMOS drivers on the clock devices complementary?
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Some of the schematics in the AD951x data sheets show an LVPECL termination scheme which is different from the classic termination often seen (50 Ω to Vs - 2V, or the Thevenin equivalent thereof). How does this work, and how did you chose 200 Ω for the resistors? Can I use 100 ohms to improve the slew rate (or jitter)?
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I have pulled SYNCB low, but I still have output from a channel. Why?
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Why can I not get the same output amplitude or rise and fall times as stated in your datasheet?
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The AD9510 datasheet says to use an external pull-up resistor on the FUNCTION pin. Why do I need this and what range of resistors will work?
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May I use the AD9540 for spread spectrum clocking?
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Can I get two clock outputs from the AD9540?
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What's the advantage of a DDS-based clock generator?
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Why does the AD9540 require special filtering on its analog output. What are the requirements of this filter?
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I'm working with optical networks - SONET/SDH. Do ADI's clock chips support these applications?
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On my board, I can't get the same low jitter numbers that are shown in the datasheet. Am I doing something wrong?
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How do you determine the bandwidth over which phase noise is integrated to obtain jitter?
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Using the "ADC SNR method", what is the equivalent bandwidth for the jitter specification?
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How do harmonic spurs in the output spectrum affect jitter (random or deterministic)?
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When a jitter number is specified without an associated bandwidth, what bandwidth should be assumed?
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How do you specify jitter?
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How do I use the clock part for jitter clean-up?
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If jitter can be calculated from phase noise measurements, is it possible to calculate phase noise from jitter numbers?
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Does jitter vary with different clock frequencies? How about phase noise?
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I sure can't measure jitter with femtosecond resolution on my scope! How do you do it? How much confidence do you have in the jitter figures that you are quoting for these parts?
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Do you guarantee performance shown in ADIsimCLK?
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Who do I contact for technical support on ADIsimCLK?
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Should I use the minimum charge pump current settings in order to minimize power?
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Can I run CMOS outputs at 5V?
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Can I use different power supply voltages for the PECL output drivers?
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Is .01 uF sufficient for power supply pin bypass?
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My application has pretty tight power consumption requirements. I am very interested in the capabilities of the AD9510, but I don't need every feature. Is it possible to turn off the unused features and save power?
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Why don't you spec psrr and cmrr in the datasheet?
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How do I get two AD951x (with PLL) to synchronize to the same reference input edge?
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I really need >10 clock outputs. Can I use multiple chips together and still guarantee that all output clocks are synchronized to REFIN?
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How do I synchronize multiple clock devices?
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What happens if I run the part in an ambient environment which exceeds 85°C?
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How can I determine the die temperature of your device?
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My circuit board has both an analog GND and a digital GND. How should I connect the AD9510 pins labeled GND?
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What PCB layout recommendations do you have for the of the exposed paddle on the bottom side of the LFCSP package?
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Does Analog Devices offer a list of manufacturers of oscillators for DDS devices?
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Where can I find some good background material on direct digital synthesis?
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RAQs index
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术语表
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