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ADF4156:  6.2 GHz Fractional-N Frequency Synthesizer

Product Details


The ADF4156 is a 6.2 GHz fractional-N frequency synthesizer that implements local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a ∑­∆ based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). The RF output phase is programmable for applications that require a particular phase relationship between the output and the reference. The ADF4156 also features cycle slip reduction circuitry, leading to faster lock times without the need for modifications to the loop filter.

Control of all on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use.


Applications
  • CATV equipment
  • Base stations for mobile radio (WiMAX, GSM, PCS, DCS, SuperCell 3G, CDMA, WCDMA)
  • Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
  • Wireless LANs, PMR
  • Communications test equipment
  • FEATURES and BENEFITS

    • RF bandwidth to 6.2 GHz
    • 2.7 V to 3.3 V power supply
    • Separate VP allows extended tuning voltage
    • Programmable fractional modulus
    • Programmable charge pump currents
    • 3-wire serial interface
    • Digital lock detect
    • Power-down mode
    • Pin compatible with the ADF4110, ADF4111, ADF4112, ADF4113, ADF4106, ADF4153, and ADF4154 frequency synthesizers
    • Programmable RF output phase
    • Loop filter design possible with ADIsimPLL
    • Cycle slip reduction for faster lock times

    Functional Block Diagram for ADF4156

    Documentation

    Title Content Type File Type
    ADF4156: 6.2 GHz Fractional-N Frequency Synthesizer Data Sheet (Rev E, 10/2013) (pdf, 415 kB) Data Sheets PDF
    AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers  (pdf, 207 kB) Application Notes PDF
    CN-0174: Low Noise, 12 GHz, Microwave Fractional-N Phase-Locked Loop (PLL) Using an Active Loop Filter and RF Prescaler  (pdf, 202 kB) Circuit Note PDF
    Fundamentals of Frequency Synthesis, Part 1: Phased Locked Loops
    The first of a two-part series on frequency synthesis, with an introduction to Phased Locked Loops. This webcast looks at the need for frequency generation, the techniques from the past present and future, and how to assess the performance of a frequency synthesis, and real world applications. Particular attention will be focused on Phase Locked Loops (PLL's) as frequency synthesizers.
    Webcasts WEBCAST
    Fundamentals of Frequency Synthesis, Part 2: Direct Digital Synthesis (DDS)
    This month we conclude our two-part series on frequency synthesis, with an introduction to Direct Digital Synthesis. We will give a basic review of how a direct digital synthesis system works, touching on the inner workings of the DDS engine at a relatively high level. We will also discuss the tradeoffs between PLL and DDS technology as a base choice for frequency synthesis needs.
    Webcasts WEBCAST
    UG-476: PLL Software Installation Guide  (pdf, 520 kB) User Guides PDF
    UG-161: PLL Frequency Synthesizer Evaluation Board  (pdf, 238 kB) User Guides PDF
    UG-171: Evaluation Board for Fractional-N PLL Frequency Synthesizer  (pdf, 332 kB) User Guides PDF
    Analog Devices Expands its Microwave IC Product Portfolio with New Family of High-Performance Voltage Controlled Oscillators (29 Oct 2012) Press Releases HTML
    RF Source Booklet  (PDF, 4353 kB)
    RF IC Product Overview - Version P (02/2014)
    Overview PDF
    Clock and Timing ICs  (pdf, 4970 kB) Overview PDF
    Why do I see reference spurs? FAQs/RAQs HTML
    Why is my phase noise shape changing when I change the PLL settings? FAQs/RAQs HTML
    Why doesn't the PLL make my reference input and the clock outputs line up? FAQs/RAQs HTML
    How do I optimize my PLL loop for the best phase noise and/or jitter? FAQs/RAQs HTML
    My loop is not locking. How do I debug this? FAQs/RAQs HTML
    How long does it take for the PLL to lock? FAQs/RAQs HTML
    Help! My PLL came unlocked over temperature. FAQs/RAQs HTML
    How do I choose between active and passive filter in PLL loop? FAQs/RAQs HTML
    Should I reference the passive filter to ground? or supply? FAQs/RAQs HTML
    How do the PLLs in the AD951x parts compare to other ADI PLLs? FAQs/RAQs HTML
    How does the clock clean-up function of the AD951x parts work? FAQs/RAQs HTML
    Why do I want to run a fast PFD frequency? FAQs/RAQs HTML
    Is it ok for me to connect the same power supply to both the charge pump and distribution power supply pins? FAQs/RAQs HTML
    Why can't I use a bandpass filter for my loop filter? FAQs/RAQs HTML
    Should I tie my loop filter to ground or PLL supply? FAQs/RAQs HTML
    The loop filter was working great until I changed the divide ratio in PLL. What happened? FAQs/RAQs HTML
    How do I use a VCO with a supply greater than 5V? FAQs/RAQs HTML
    What suppliers do you recommend for VCO/VCXOs? FAQs/RAQs HTML
    Do VCXOs have better phase noise and jitter performance than VCOs? FAQs/RAQs HTML
    How do I know which VCO will work best with the AD9510? FAQs/RAQs HTML
    Is there an advantage to running a higher VCO frequency than the output frequency? FAQs/RAQs HTML
    How do I determine if a VCO is good enough for my purpose? FAQs/RAQs HTML
    Is there any difference between the nature of an oscillator's phase noise and the phase noise from a clock chip? FAQs/RAQs HTML
    Do different divide ratios cause variations in jitter? FAQs/RAQs HTML
    I have a clocking scheme which requires several different division ratios simultaneously. I have a frequency plan, but I'm concerned about crosstalk. How much of a problem is this with your clock distribution chips? FAQs/RAQs HTML
    Do divide ratios change the propagation delay? FAQs/RAQs HTML
    I want to use the phase offset feature on the AD9510 dividers to generate two signals 90° out of phase. How accurate is the phase offset? FAQs/RAQs HTML
    On the AD951x clock ICs, does the phase offset (coarse delay) affect the jitter? FAQs/RAQs HTML
    Why doesn't the mini-divider support the divide ratio I want? FAQs/RAQs HTML
    I want to use the variable delay adjust, but the jitter is too high. What can I do? FAQs/RAQs HTML
    I changed the coarse phase adjust in the evaluation software, but nothing happened. What's going on? FAQs/RAQs HTML
    What is the difference between the coarse phase adjust and the fine delay adjust? FAQs/RAQs HTML
    What is the fine delay adjust which is available on certain LVDS/CMOS outputs? FAQs/RAQs HTML
    Does the fine delay adjust affect the jitter? FAQs/RAQs HTML
    Why is the fine delay adjust not available on all the outputs? FAQs/RAQs HTML
    Is there a way to cause Input/Output rising edges to be synchronous (zero delay) with the AD9510/11? FAQs/RAQs HTML
    Will the AD9510 work without a reference input signal? FAQs/RAQs HTML
    What are the best clock sources for a distribution-only design? FAQs/RAQs HTML
    I am not using the CLK1 input on the AD9510. Can I just leave it floating? FAQs/RAQs HTML
    How good does my input signal need to be? FAQs/RAQs HTML
    I turned off my reference but the Digital Lock Detect (DLD) still says I'm locked. FAQs/RAQs HTML
    Can I shift the threshold on clocks for single-ended inputs? FAQs/RAQs HTML
    The reference input is differential, but my reference is single-ended. Do I need to convert to differential to drive the AD9510? FAQs/RAQs HTML
    Will differential or single-ended inputs/outputs improve my jitter? FAQs/RAQs HTML
    Why should I use differential rather than single-ended? FAQs/RAQs HTML
    How do I feed a single-ended signal into a differential input? FAQs/RAQs HTML
    Why do you recommend AC coupling, rather than DC coupling, at the clock inputs? FAQs/RAQs HTML
    Are the ADI clock parts stand-alone clock sources or do I still have to buy a clock source to drive these parts? FAQs/RAQs HTML
    Which provides better performance - a clock source with sinewave output, or one with differential square wave outputs? FAQs/RAQs HTML
    On the AD9510, what is the relationship between clock output jitter and CLK1/CLK2 input slew rate? FAQs/RAQs HTML
    I'm trying to write to the part in single-byte mode, but I can't write anything. What am I doing wrong? FAQs/RAQs HTML
    Can I use the 951X clocks to drive a mixer (RF LO)? FAQs/RAQs HTML
    My applications are RF, not for clocking data converters. Can ADI's 951X ICs be used for RF applications? FAQs/RAQs HTML
    I have an input present at the clock input, but I'm not seeing an output? FAQs/RAQs HTML
    What happens to the AD9510/11 clock outputs if the Reference Input (REFIN) signal goes away? FAQs/RAQs HTML
    What clock frequency comes out of the AD9510 outputs when you first apply power to the device? FAQs/RAQs HTML
    Is it possible to impedance match a clock output if it is heavily loaded? (e.g. CL=100pF) FAQs/RAQs HTML
    I ran the AD9510 outputs at 1.4 GHz and they seem to work fine. Is there a problem running them at 1.4 GHz? FAQs/RAQs HTML
    What should I do with unused channels on the AD9510? FAQs/RAQs HTML
    Can I tri-state the AD9510 outputs? FAQs/RAQs HTML
    On the AD9510, how can I make sure that the duty cycle of output clocks stays within 40% to 60% duty cycle window? FAQs/RAQs HTML
    What is the effect of distributing harmonically related clocks (on chip or on board) in terms of jitter? FAQs/RAQs HTML
    Is there any reason to use a transformer on a differential clock output to obtain a "clean" single-ended clock output? FAQs/RAQs HTML
    What are some of the advantages/disadvantages of using LVPECL vs. LVDS outputs? FAQs/RAQs HTML
    Does the AD9510 support 2.5V PECL? FAQs/RAQs HTML
    How much bandwidth is required to process a PECL or LVDS output? FAQs/RAQs HTML
    If I use only one of the PECL differential outputs and the unused output is terminated in 50Ω, how will this affect the phase noise or jitter of the single-ended output? FAQs/RAQs HTML
    If I change the level of PECL output, does it affect the jitter? FAQs/RAQs HTML
    What is the best way to terminate LVPECL outputs to get lowest jitter? FAQs/RAQs HTML
    Is it okay to AC-couple PECL or LVDS outputs? FAQs/RAQs HTML
    What is the fan-out capability of the CMOS, LVDS, and LVPECL outputs? FAQs/RAQs HTML
    What is the proper termination (value and location) for outputs? FAQs/RAQs HTML
    Are outputs short-circuit protected? FAQs/RAQs HTML
    Are the CMOS drivers on the clock devices complementary? FAQs/RAQs HTML
    Some of the schematics in the AD951x data sheets show an LVPECL termination scheme which is different from the classic termination often seen (50 Ω to Vs - 2V, or the Thevenin equivalent thereof). How does this work, and how did you chose 200 Ω for the resistors? Can I use 100 ohms to improve the slew rate (or jitter)? FAQs/RAQs HTML
    I have pulled SYNCB low, but I still have output from a channel. Why? FAQs/RAQs HTML
    Why can I not get the same output amplitude or rise and fall times as stated in your datasheet? FAQs/RAQs HTML
    The AD9510 datasheet says to use an external pull-up resistor on the FUNCTION pin. Why do I need this and what range of resistors will work? FAQs/RAQs HTML
    May I use the AD9540 for spread spectrum clocking? FAQs/RAQs HTML
    Can I get two clock outputs from the AD9540? FAQs/RAQs HTML
    What's the advantage of a DDS-based clock generator? FAQs/RAQs HTML
    Why does the AD9540 require special filtering on its analog output. What are the requirements of this filter? FAQs/RAQs HTML
    I'm working with optical networks - SONET/SDH. Do ADI's clock chips support these applications? FAQs/RAQs HTML
    On my board, I can't get the same low jitter numbers that are shown in the datasheet. Am I doing something wrong? FAQs/RAQs HTML
    How do you determine the bandwidth over which phase noise is integrated to obtain jitter? FAQs/RAQs HTML
    Using the "ADC SNR method", what is the equivalent bandwidth for the jitter specification? FAQs/RAQs HTML
    How do harmonic spurs in the output spectrum affect jitter (random or deterministic)? FAQs/RAQs HTML
    When a jitter number is specified without an associated bandwidth, what bandwidth should be assumed? FAQs/RAQs HTML
    How do you specify jitter? FAQs/RAQs HTML
    How do I use the clock part for jitter clean-up? FAQs/RAQs HTML
    If jitter can be calculated from phase noise measurements, is it possible to calculate phase noise from jitter numbers? FAQs/RAQs HTML
    Does jitter vary with different clock frequencies? How about phase noise? FAQs/RAQs HTML
    I sure can't measure jitter with femtosecond resolution on my scope! How do you do it? How much confidence do you have in the jitter figures that you are quoting for these parts? FAQs/RAQs HTML
    Do you guarantee performance shown in ADIsimCLK? FAQs/RAQs HTML
    Who do I contact for technical support on ADIsimCLK? FAQs/RAQs HTML
    Should I use the minimum charge pump current settings in order to minimize power? FAQs/RAQs HTML
    Can I run CMOS outputs at 5V? FAQs/RAQs HTML
    Can I use different power supply voltages for the PECL output drivers? FAQs/RAQs HTML
    Is .01 uF sufficient for power supply pin bypass? FAQs/RAQs HTML
    My application has pretty tight power consumption requirements. I am very interested in the capabilities of the AD9510, but I don't need every feature. Is it possible to turn off the unused features and save power? FAQs/RAQs HTML
    Why don't you spec psrr and cmrr in the datasheet? FAQs/RAQs HTML
    How do I get two AD951x (with PLL) to synchronize to the same reference input edge? FAQs/RAQs HTML
    I really need >10 clock outputs. Can I use multiple chips together and still guarantee that all output clocks are synchronized to REFIN? FAQs/RAQs HTML
    How do I synchronize multiple clock devices? FAQs/RAQs HTML
    What happens if I run the part in an ambient environment which exceeds 85°C? FAQs/RAQs HTML
    How can I determine the die temperature of your device? FAQs/RAQs HTML
    My circuit board has both an analog GND and a digital GND. How should I connect the AD9510 pins labeled GND? FAQs/RAQs HTML
    What PCB layout recommendations do you have for the of the exposed paddle on the bottom side of the LFCSP package? FAQs/RAQs HTML
    What is a PLL Synthesizers and how is it used? FAQs/RAQs HTML
    RAQs index Rarely Asked Questions HTML
    Glossary of EE Terms Glossary HTML

    Design Tools,Models,Drivers & Software

    Title Content Type File Type
    ADIsimRF
    ADI’s ADIsimRF design tool provides calculations for the most important parameters within the RF signal chain, including cascaded gain, noise figure, IP3, P1dB, and total power consumption.
    ADIsim Design/Simulation Tools HTML
    ADIsimPLL™- Version 3.60.10
    ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.
    ADIsim Design/Simulation Tools HTML
    BeMicro FPGA Project for ADF4156 with Nios driver FPGA HDL HTML
    ADF4156 FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design FPGA HDL HTML
    Fractional-N Software  (zip, 12062 kB) Evaluation Software ZIP

    Evaluation Kits & Symbols & Footprints

    Evaluation Boards & KitsView the Evaluation Boards and Kits page for documentation and purchasing

    Symbols and Footprints— Analog Devices offers Symbols & Footprints which are compatible with a large set of today’s CAD systems for broader and easier support.

    Product Recommendations & Reference Designs

    Engineered. Tested. Ready to Integrate.
    Learn More

    Companion Products

    Suggested Complementary Products


    Recommended Divide-by-4 Prescaler for the ADF4156

    • For a low noise, low power, fixed RF block, we recommend the ADF5001.
    Recommended PLL Active Filter for the ADF4156
    • For an ultralow noise, rail-to-rail amplifier, we recommend the OP184.
    Recommended Linear Regulators for the ADF4156
    • For ultralow noise, 3V applications,150mA output, we recommend the ADP150.
    • For ultalow noise, 3V applications, 200mA output, we recommend the ADP151.
    • For high accuracy, 5V applications, we recommend the ADP3334.
    • For a step up, 3V to 5V regulator, we recommend the ADP1613.
    Recommended Power Solutions
    • For selecting voltage regulator products, use ADIsimPower.

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    Price, packaging, availability

    ADF4156 Model Options
    Model Package Pins Temp.
    Range
    Packing,
    Qty
    Price*(100-499) Price*1000 pcs RoHS View PCN/ PDN Check Inventory/
    Purchase/Sample
    ADF4156BCPZ Status: Production 20 ld LFCSP 4x4mm (2.1EP) 20 Ind Tray, 490 $3.17 $2.83 Y  Material Info PCN Purchase Sample
    ADF4156BCPZ-RL Status: Production 20 ld LFCSP 4x4mm (2.1EP) 20 Ind Reel, 5000 - $2.83 Y  Material Info PCN Purchase
    ADF4156BCPZ-RL7 Status: Production 20 ld LFCSP 4x4mm (2.1EP) 20 Ind Reel, 1500 - $2.83 Y  Material Info PCN Purchase
    ADF4156BRUZ Status: Production 16 ld TSSOP 16 Ind Tube, 96 $3.17 $2.83 Y  Material Info PCN Purchase Sample
    ADF4156BRUZ-RL Status: Production 16 ld TSSOP 16 Ind Reel, 2500 - $2.83 Y  Material Info PCN Purchase
    ADF4156BRUZ-RL7 Status: Production 16 ld TSSOP 16 Ind Reel, 1000 - $2.83 Y  Material Info PCN Purchase
    Price Table Help

    The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.

    ADF4156 Evaluation Board
    Model Description Price RoHS View PCN/ PDN Check Inventory/
    Purchase/Sample
    EV-ADF4156SD1Z Status: Production Evaluation Board $151.80 Yes -
    EVAL-SDP-CS1Z Status: Production SDP-S Controller Board - Interface to EV-ADF4156SD1Z $49.00 Yes -

    Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.

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