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AD6659:  Dual IF Receiver

Product Details

Product Status:Recommended for New Designs

The AD6659 is a mixed-signal, dual-channel IF receiver supporting radio topologies requiring two receiver signal paths, such as in main/diversity or direct conversion. This communications systems processor consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. It is designed to support various commu-nications applications where high dynamic range performance and small size are desired.

The high dynamic range ADC core features a multistage differential pipelined architecture with integrated output error correction logic. Each ADC features a wide bandwidth switch capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations.

Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist region. The device supports two different output modes selectable via the serial port interface (SPI).

With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6659 supports enhanced SNR performance within a limited region of the Nyquist bandwidth while maintaining a 12-bit output resolution. The NSR block is programmed to provide a bandwidth of 20% of the sample clock. For example, with a sample clock rate of 80 MSPS, the AD6659 can achieve up to 81.5 dBFS SNR for a 16 MHz bandwidth at 9.7 MHz AIN.

With the NSR block disabled, the ADC data is provided directly to the output with an output resolution of 12 bits. The AD6659 can achieve up to 72 dBFS SNR for the entire Nyquist bandwidth when operated in this mode.

After digital processing, output data is routed into two 12-bit output ports that support 1.8 V or 3.3 V CMOS levels. The AD6659 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of the main and diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods.

The AD6659 also incorporates an optional integrated dc offset correction and quadrature error correction (QEC) block that corrects for gain and phase mismatch between the two channels. This functional block proves invaluable in complex signal processing applications such as direct conversion receivers.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).

A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.

The digital output data is presented in offset binary, gray code, or twos complement format. A data clock output (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported, and output data can be multiplexed onto a single output bus.

The AD6659 is available in a 64-lead, RoHS-compliant LFCSP, and it is specified over the industrial temperature range (−40°C to +85°C).

  • Communications
  • Diversity radio systems
  • Multimode digital receivers

  • I/Q demodulation systems
  • Smart antenna systems
  • Battery-powered instruments
  • General-purpose software radios


  • 12-bit, 80 MSPS output data rate per channel
  • 1.8 V analog supply operation (AVDD)
  • 1.8 V to 3.3 V output supply (DRVDD)
  • Integrated noise shaping requantizer (NSR)
  • Integrated quadrature error correction (QEC)
  • Performance with NSR enabled
    SNR = 81 dBFS in 16 MHz band up to 30 MHz at 80 MSPS
  • Performance with NSR disabled
    SNR = 72 dBFS up to 70 MHz at 80 MSPS
    SFDR = 90 dBc up to 70 MHz input at 80 MSPS
  • Low power: 98 mW per channel at 80 MSPS
  • Differential input with 700 MHz bandwidth
  • On-chip voltage reference and sample-and-hold circuit
  • 2 V p-p differential analog input
  • Serial port control options
    (For additonal details, please the data sheet)

Functional Block Diagram for AD6659


Title Content Type File Type
AD6659: Dual IF Receiver Data Sheet (Rev A, 02/2010) (pdf, 1004 kB) Data Sheets PDF
AN-878: High Speed ADC SPI Control Software  (pdf, 585 kB) Application Notes PDF
AN-935: Designing an ADC Transformer-Coupled Front End  (pdf, 363 kB) Application Notes PDF
AN-742: Frequency Domain Response of Switched-Capacitor ADCs  (pdf, 401 kB) Application Notes PDF
MS-2210: Designing Power Supplies for High Speed ADC  (pdf, 327 kB) Technical Articles PDF
RAQs index Rarely Asked Questions HTML
Glossary of EE Terms Glossary HTML

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Product Recommendations & Reference Designs

Companion Products

Suggested Companion Products

Recommended ADC Drivers for the AD6659
  • For frequencies in the second Nyquist zone, we recommend the AD8352 differential driver.
Recommended Clock Drivers for the AD6659 Recommended External Reference for the AD6659
  • For improved thermal drift and gain accuracy, we recommend the ADR130 (1V reference).
Recommended Power Solutions

  • For selecting voltage regulator products, use ADIsimPower.

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The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.

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