AD9652

16-bit, 310 MSPS, 3.3/1.8 V Dual Analog-to-Digital Converter (ADC)

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Recommended for New Designs

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Overview

Features and Benefits
Product Details

Features and Benefits

High Dynamic Range
SNR = 75.0 dBFS at 70 MHz
(AIN = −1 dBFS)
SFDR = 87 dBc at 70 MHz
(AIN = −1 dBFS)
Excellent IF Sampling Performance
SNR = 73.7 dBFS at 170 MHz (A_IN = −1 dBFS)
SFDR = 85 dBc at 170 MHz (A_IN = −1 dBFS)
Full power bandwidth of 465 MHz
Energy saving power-down modes
SYNC input allows multichip synchronization

Differential clock input receiver with 1, 2, 4, and 8 integer inputs (clock divider input accepts up to 1.24 GHz)
Internal ADC clock duty cycle stabilizer
Total power consumption:
2.16 W 3.3 V and 1.8 V supply voltages
DDR LVDS (ANSI-644 levels) outputs
Serial port control
On-chip 3.3 V buffer
Programmable input span of 2 V_P-P to 2.5 V_P-P (default)

Product Details

The AD9652 is a dual, 16-bit analog-to-digital converter (ADC) with sampling speeds of up to 310 MSPS. It is designed to support demanding, high speed signal processing applications that require exceptional dynamic range over a wide input frequency range (up to 465 MHz). Its exceptional low noise floor of −157.6 dBFS and large signal spurious-free dynamic range (SFDR) performance (exceeding 85 dBFS, typical) allows low level signals to be resolved in the presence of large signals.

The dual ADC cores feature a multistage, pipelined architecture with integrated output error correction logic. A high performance on-chip buffer and internal voltage reference simplify the inter-face to external driving circuitry while preserving the exceptional performance of the ADC.

The AD9652 can support input clock frequencies of up to 1.24 GHz with a 1, 2, 4, and 8 integer clock divider used to generate the ADC sample clock. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle. The 16-bit output data (with an overrange bit) from each ADC is interleaved onto a single LVDS output port along with a double data rate (DDR) clock. Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.

The AD9652 is available in a 144-ball CSP_BGA and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by pending U.S. patents.

PRODUCT HIGHLIGHTS

Integrated dual, 16-bit, 310 MSPS ADCs.
On-chip buffer simplifies ADC driver interface.
Operation from a 3.3 V and 1.8 V supply and a separate digital output driver supply accommodating LVDS outputs.
Proprietary differential input maintains excellent SNR performance for input frequencies of up to 485 MHz.
SYNC input allows synchronization of multiple devices.
Three-wire, 3.3 V or 1.8 V SPI port for register programming and readback.

APPLICATIONS

Miltary radar and communications
Multimode digital receivers (3G or 4G)
Test and Instrumentation
Smart antenna systems

Product Categories

A/D Converters (ADC)
- Standard High Speed A/D Converters

Markets and Technologies

Aerospace and Defense (1)
- Aerospace and Defense Radar Systems

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Product Lifecycle Recommended for New Designs

This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.

Evaluation Kits (3)

EVAL-AD9652

AD9652 Evaluation Board

AD-FMCOMMS6-EBZ

AD-FMCOMMS6-EBZ Evaluation Board

HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

EVAL-AD9652

View Detailed Evaluation Kit Information

The AD9652-310EBZ is an evaluation board for the AD9652, dual, 16-bit ADC. This reference design provides all of the support circuitry to operate devices in their various modes and configurations, It is designed to interface directly with the HSC-ADC-EVALCZ data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device’s hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI controller software package is also compatible with this hardware and allows the user to access the SPI programmable features of the AD9652.

The AD9652 data sheet provides additional information related to device configuration and performance and should be consulted when using these tools. All documents and Visual Analog and SPI Controller are available at the High Speed ADC Evaluation Boards page. For additional information or questions, please email highspeedproductssupport@analog.com.

Features & Benefits

Full featured evaluation board for the AD9652
SPI interface for setup and control
External clocking option
Balun/transformer or amplifier input drive option
LDO regulator or switching power supply options
VisualAnalog^® and SPI controller software interfaces

Resources

Evaluating the AD9652 Analog-to-Digital Converters

WIKI

AD-FMCOMMS6-EBZ

View Detailed Evaluation Kit Information

The AD-FMCOMMS6-EBZ eval board is a 400MHz to 4.4GHz receiver based on the AD9652 dual 16bit analog to digital converter, the ADL5566 High Dynamic Range RF/IF Dual Differential Amplifier and the ADL5380 quadrature demodulator.

This is an I and Q demodulation approach to direct convert (also known as a homodyne or zero IF) receiver architecture. Direct conversion radios perform just one frequency translation compared to a super-heterodyne receiver that can perform several frequency translations. One frequency translation is advantageous because it:

Reduces receiver complexity and the number of stages needed, increasing performance and reducing power consumption
Avoids image rejection issues and unwanted mixing

This topology will provide image rejection and early implementation of the differential signal environment. There is an amplification stage to maintain the full-scale input to the ACD. The local oscillator and ADC clock are on board and share the same reference signal prevent smearing. The form factor is VITA57 compliant and all of the DC power is routed from the data capture board through an FMC connector. This evaluation board demonstrates a high performance receiver signal chain aimed at military and commercial radar using “commercial off the shelf” (COTS) components. The overall circuit has a bandwidth of 220MHz with a pass band flatness of +/_ 1.0 dB. The SNR and SFDR measured at an IF of 145MHz are 64dB and 75dBc, respectively.

Features & Benefits

Reduces receiver complexity and the number of stages needed, increasing performance and reducing power consumption
Avoids image rejection issues and unwanted mixing

Resources

AD-FMCOMMS6-EBZ User Guide

WIKI

HSC-ADC-EVALCZ

View Detailed Evaluation Kit Information

The HSC-ADC-EVALCZ high speed converter evaluation platform uses an FPGA based buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The board is connected to the PC through a USB port and is used with VisualAnalog^® to quickly evaluate the performance of high speed ADCs. The evaluation kit is easy to set up. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC.

Features & Benefits

64kB FIFO Depth
Works with single and multi-channel ADCs
Use with VisualAnalog^® software
Based on Virtex-4 FPGA
May require adaptor to interface with some ADC eval boards
Allows programming of SPI control Up to 644 MSPS SDR / 800MSPS DDR Encode Rates on each channel
DDR Encode Rates on each channel

Resources

High Speed ADC USB FPGA Evaluation Kit, EVALC

PDF

2.1 M

Software

Documentation & Resources

3rd Party Solutions

Delphi Engineering-ADF-O310, Octal Channel 310 MS/s 16 Bit ADC FMC Module
9/11/2019

Data Sheets

AD9652: 16-Bit, 310 MSPS, 3.3 V/1.8 V Dual Analog-to-Digital Converter (ADC) Data Sheet (Rev. C)
4/1/2014
PDF

User Guides

Evaluating the AD9652 Analog-to-Digital Converters
5/6/2014

WIKI

Videos

AD9652:Dual, 310 MSPS ADC with Better SNR & Higher Bandwidth
11/28/2018

Webcasts

Tools & Simulations

Virtual Eval - BETA

Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.

Virtual Eval Tool - BETA

MathWorks®

AD9652 Simulink ADIsimADC Model

Product Recommendations

AD9652 Companion Parts

Recommended Driver Amplifiers

For IF sampling and digitally controlled variable gain: AD8375, AD8376.
For baseband applications: ADL5566, ADA4938-2, ADA4930-2.

Recommended Clock Drivers

For differential LVPECL, CMOS or LVDS signals: AD9530, AD9525.

Design Resources

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.

Part Number	Material Declaration	Reliability Data	Pin/Package Drawing	CAD Symbols, Footprints & 3D Models
AD9652BBCZ-310	Material Declaration	Reliability Data	144-Ball CSPBGA (10mm x 10mm)	Ultra Librarian SamacSys
AD9652BBCZRL7-310	Material Declaration	Reliability Data	144-Ball CSPBGA (10mm x 10mm)	Ultra Librarian SamacSys
Wafer Fabrication Data

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Support & Discussions

ad9652 Discussions

RE: provide me a demo code in Verilog of AD9652

20 week(s) ago in Speed ADCs

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Evaluation Boards

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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.