AD9652
Info : RECOMMENDED FOR NEW DESIGNS
searchIcon
cartIcon

AD9652

16-bit, 310 MSPS, 3.3/1.8 V Dual Analog-to-Digital Converter (ADC)

Show More showmore-icon

Info : RECOMMENDED FOR NEW DESIGNS tooltip
Info : RECOMMENDED FOR NEW DESIGNS tooltip
Part Details
Part Models 2
1ku List Price Starting From $296.93
Features
  • High Dynamic Range
    SNR = 75.0 dBFS at 70 MHz
    (AIN = −1 dBFS)
    SFDR = 87 dBc at 70 MHz
    (AIN = −1 dBFS)
  • Excellent IF Sampling Performance
    SNR = 73.7 dBFS at 170 MHz (AIN = −1 dBFS)
    SFDR = 85 dBc at 170 MHz (AIN = −1 dBFS)
    Full power bandwidth of 465 MHz
  • Energy saving power-down modes
  • SYNC input allows multichip synchronization
  • Differential clock input receiver with 1, 2, 4, and 8 integer inputs (clock divider input accepts up to 1.24 GHz)
  • Internal ADC clock duty cycle stabilizer
  • Total power consumption:
    2.16 W 3.3 V and 1.8 V supply voltages
  • DDR LVDS (ANSI-644 levels) outputs
  • Serial port control
  • On-chip 3.3 V buffer
    Programmable input span of 2 VP-P to 2.5 VP-P (default)
Additional Details
show more Icon

The AD9652 is a dual, 16-bit analog-to-digital converter (ADC) with sampling speeds of up to 310 MSPS. It is designed to support demanding, high speed signal processing applications that require exceptional dynamic range over a wide input frequency range (up to 465 MHz). Its exceptional low noise floor of −157.6 dBFS and large signal spurious-free dynamic range (SFDR) performance (exceeding 85 dBFS, typical) allows low level signals to be resolved in the presence of large signals.

The dual ADC cores feature a multistage, pipelined architecture with integrated output error correction logic. A high performance on-chip buffer and internal voltage reference simplify the inter-face to external driving circuitry while preserving the exceptional performance of the ADC.

The AD9652 can support input clock frequencies of up to 1.24 GHz with a 1, 2, 4, and 8 integer clock divider used to generate the ADC sample clock. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle. The 16-bit output data (with an overrange bit) from each ADC is interleaved onto a single LVDS output port along with a double data rate (DDR) clock. Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.

The AD9652 is available in a 144-ball CSP_BGA and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by pending U.S. patents.

PRODUCT HIGHLIGHTS

  1. Integrated dual, 16-bit, 310 MSPS ADCs.
  2. On-chip buffer simplifies ADC driver interface.
  3. Operation from a 3.3 V and 1.8 V supply and a separate digital output driver supply accommodating LVDS outputs.
  4. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 485 MHz.
  5. SYNC input allows synchronization of multiple devices.
  6. Three-wire, 3.3 V or 1.8 V SPI port for register programming and readback.

APPLICATIONS

  • Miltary radar and communications
  • Multimode digital receivers (3G or 4G)
  • Test and Instrumentation
  • Smart antenna systems
Part Models 2
1ku List Price Starting From $296.93

close icon
Documentation

Documentation

Video

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
AD9652BBCZ-310
  • HTML
  • HTML
AD9652BBCZRL7-310
  • HTML
  • HTML

Filter by Model

reset

Reset Filters

Part Models

Product Lifecycle

PCN

Feb 11, 2015

- 14_0254

Bump and Assembly Transfer of Select 10x10 and 12x12 Flip Chip Products

Filter by Model

reset

Reset Filters

Part Models

Product Lifecycle

PCN

Feb 11, 2015

- 14_0254

arrow down

Bump and Assembly Transfer of Select 10x10 and 12x12 Flip Chip Products

Software & Part Ecosystem

Software & Part Ecosystem

Can't find the software or driver you need?

Request a Driver/Software
Evaluation Kit

Evaluation Kits 3

reference details image

EVAL-AD9652

AD9652 Evaluation Board

zoom

EVAL-AD9652

AD9652 Evaluation Board

AD9652 Evaluation Board

Features and Benefits

  • Full featured evaluation board for the AD9652
  • SPI interface for setup and control
  • External clocking option
  • Balun/transformer or amplifier input drive option
  • LDO regulator or switching power supply options
  • VisualAnalog® and SPI controller software interfaces

Product Detail

The AD9652-310EBZ is an evaluation board for the AD9652, dual, 16-bit ADC. This reference design provides all of the support circuitry to operate devices in their various modes and configurations, It is designed to interface directly with the HSC-ADC-EVALCZ data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device’s hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI controller software package is also compatible with this hardware and allows the user to access the SPI programmable features of the AD9652.

The AD9652 data sheet provides additional information related to device configuration and performance and should be consulted when using these tools. All documents and Visual Analog and SPI Controller are available at the High Speed ADC Evaluation Boards page. For additional information or questions, please email highspeedproductssupport@analog.com.

reference details image

HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

zoom

HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

FPGA-Based Data Capture Kit

Features and Benefits

  • 64kB FIFO Depth
  • Works with single and multi-channel ADCs
  • Use with VisualAnalog® software
  • Based on Virtex-4 FPGA
  • May require adaptor to interface with some ADC eval boards
  • Allows programming of SPI control Up to 644 MSPS SDR / 800MSPS DDR Encode Rates on each channel
  • DDR Encode Rates on each channel

Product Detail

The HSC-ADC-EVALCZ high speed converter evaluation platform uses an FPGA based buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The board is connected to the PC through a USB port and is used with VisualAnalog® to quickly evaluate the performance of high speed ADCs. The evaluation kit is easy to set up. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC.
reference details image

AD-FMCOMMS6-EBZ

AD-FMCOMMS6-EBZ Evaluation Board

zoom

AD-FMCOMMS6-EBZ

AD-FMCOMMS6-EBZ Evaluation Board

AD-FMCOMMS6-EBZ Evaluation Board

Features and Benefits

  • Reduces receiver complexity and the number of stages needed, increasing performance and reducing power consumption 
  • Avoids image rejection issues and unwanted mixing 

Product Detail

The AD-FMCOMMS6-EBZ eval board is a 400MHz to 4.4GHz receiver based on the AD9652 dual 16bit analog to digital converter, the ADL5566 High Dynamic Range RF/IF Dual Differential Amplifier and the ADL5380 quadrature demodulator.

This is an I and Q demodulation approach to direct convert (also known as a homodyne or zero IF) receiver architecture. Direct conversion radios perform just one frequency translation compared to a super-heterodyne receiver that can perform several frequency translations. One frequency translation is advantageous because it:

  • Reduces receiver complexity and the number of stages needed, increasing performance and reducing power consumption
  • Avoids image rejection issues and unwanted mixing


This topology will provide image rejection and early implementation of the differential signal environment. There is an amplification stage to maintain the full-scale input to the ACD. The local oscillator and ADC clock are on board and share the same reference signal prevent smearing. The form factor is VITA57 compliant and all of the DC power is routed from the data capture board through an FMC connector. This evaluation board demonstrates a high performance receiver signal chain aimed at military and commercial radar using “commercial off the shelf” (COTS) components. The overall circuit has a bandwidth of 220MHz with a pass band flatness of +/_ 1.0 dB. The SNR and SFDR measured at an IF of 145MHz are 64dB and 75dBc, respectively.


Tools & Simulations

Tools & Simulations 2

Recently Viewed