AD9652
RECOMMENDED FOR NEW DESIGNS16-bit, 310 MSPS, 3.3/1.8 V Dual Analog-to-Digital Converter (ADC)
- Part Models
- 2
- 1ku List Price
- Starting From $296.93
Part Details
- High Dynamic Range
SNR = 75.0 dBFS at 70 MHz
(AIN = −1 dBFS)
SFDR = 87 dBc at 70 MHz
(AIN = −1 dBFS) - Excellent IF Sampling Performance
SNR = 73.7 dBFS at 170 MHz (AIN = −1 dBFS)
SFDR = 85 dBc at 170 MHz (AIN = −1 dBFS)
Full power bandwidth of 465 MHz - Energy saving power-down modes
- SYNC input allows multichip synchronization
- Differential clock input receiver with 1, 2, 4, and 8 integer inputs (clock divider input accepts up to 1.24 GHz)
- Internal ADC clock duty cycle stabilizer
- Total power consumption:
2.16 W 3.3 V and 1.8 V supply voltages - DDR LVDS (ANSI-644 levels) outputs
- Serial port control
- On-chip 3.3 V buffer
Programmable input span of 2 VP-P to 2.5 VP-P (default)
The AD9652 is a dual, 16-bit analog-to-digital converter (ADC) with sampling speeds of up to 310 MSPS. It is designed to support demanding, high speed signal processing applications that require exceptional dynamic range over a wide input frequency range (up to 465 MHz). Its exceptional low noise floor of −157.6 dBFS and large signal spurious-free dynamic range (SFDR) performance (exceeding 85 dBFS, typical) allows low level signals to be resolved in the presence of large signals.
The dual ADC cores feature a multistage, pipelined architecture with integrated output error correction logic. A high performance on-chip buffer and internal voltage reference simplify the inter-face to external driving circuitry while preserving the exceptional performance of the ADC.
The AD9652 can support input clock frequencies of up to 1.24 GHz with a 1, 2, 4, and 8 integer clock divider used to generate the ADC sample clock. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle. The 16-bit output data (with an overrange bit) from each ADC is interleaved onto a single LVDS output port along with a double data rate (DDR) clock. Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.
The AD9652 is available in a 144-ball CSP_BGA and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by pending U.S. patents.
PRODUCT HIGHLIGHTS
- Integrated dual, 16-bit, 310 MSPS ADCs.
- On-chip buffer simplifies ADC driver interface.
- Operation from a 3.3 V and 1.8 V supply and a separate digital output driver supply accommodating LVDS outputs.
- Proprietary differential input maintains excellent SNR performance for input frequencies of up to 485 MHz.
- SYNC input allows synchronization of multiple devices.
- Three-wire, 3.3 V or 1.8 V SPI port for register programming and readback.
APPLICATIONS
- Miltary radar and communications
- Multimode digital receivers (3G or 4G)
- Test and Instrumentation
- Smart antenna systems
Documentation
Data Sheet 1
User Guide 1
Video 1
3rd Party Solutions 1
Device Drivers 1
Webcast 2
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9652BBCZ-310 | 144-Ball CSPBGA (10mm x 10mm) | ||
| AD9652BBCZRL7-310 | 144-Ball CSPBGA (10mm x 10mm) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
| No Match Found | ||
|
Feb 11, 2015 - 14_0254 Bump and Assembly Transfer of Select 10x10 and 12x12 Flip Chip Products |
||
| AD9652BBCZ-310 | PRODUCTION | |
| AD9652BBCZRL7-310 | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Software Resources
Device Drivers 1
Evaluation Software 0
Can't find the software or driver you need?
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock Generation Devices 2 | ||
| AD9530 | RECOMMENDED FOR NEW DESIGNS | 4 CML Output, Low Jitter Clock Generator with an Integrated 5.4 GHz VCO |
| AD9525 | RECOMMENDED FOR NEW DESIGNS | Low Jitter Clock Generator Eight LVPECL Outputs |
| Digital Control VGAs 2 | ||
| AD8375 | PRODUCTION | Ultralow Distortion IF VGA |
| AD8376 | RECOMMENDED FOR NEW DESIGNS | Ultralow Distortion IF Dual VGA |
| Fully Differential Amplifiers 1 | ||
| ADL5566 | RECOMMENDED FOR NEW DESIGNS | 4.5 GHz Ultrahigh Dynamic Range, Dual Differential Amplifier |
| Single-Ended to Differential Amplifiers 2 | ||
| ADA4938-2 | RECOMMENDED FOR NEW DESIGNS | Ultralow Distortion Differential ADC Driver (Dual) |
| ADA4930-2 | RECOMMENDED FOR NEW DESIGNS | Ultralow Noise Drivers for Low Voltage ADCs |
Tools & Simulations
Virtual Eval - BETA
Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.
Open ToolAD9652 Simulink ADIsimADC Model
Open ToolEvaluation Kits
AD9652 Evaluation Board
Resources
FPGA-Based Data Capture Kit
Resources
Software
AD-FMCOMMS6-EBZ Evaluation Board