AD9609
Info: : PRODUCTION
searchIcon
cartIcon

AD9609

10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter

Show More showmore-icon

Info: : PRODUCTION tooltip
Info: : PRODUCTION tooltip
Part Details
Part Models 8
1ku List Price Starting From $4.63
Features
  • 1.8 V analog supply operation
  • 1.8 V to 3.3 V output supply
  • SNR
    • 61.5 dBFS at 9.7 MHz input
    • 61.0 dBFS at 200 MHz input
  • SFDR
    • 75 dBc at 9.7 MHz input
    • 73 dBc at 200 MHz input
  • Low power
    • 45 mW at 20 MSPS
    • 76 mW at 80 MSPS
  • Differential input with 700 MHz bandwidth
  • On-chip voltage reference and sample-and-hold circuit
  • 2 V p-p differential analog input
  • DNL = ±0.10 LSB
  • Serial port control options
    • Offset binary, gray code, or twos complement data format
    • Optional clock duty cycle stabilizer
    • Integer 1-to-8 input clock divider
    • Built-in selectable digital test pattern generation
    • Energy-saving power-down modes
    • Data clock out with programmable clock and data alignment
Additional Details
show more Icon

The AD9609 is a monolithic, single channel 1.8 V supply, 10-bit, 20/40/65/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.

The product uses multistage differential pipeline architecture with output error correction logic to provide 10-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).

A differential clock input with selectable internal 1 to 8 divide ratio controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.

The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported.

The AD9609 is available in a 32-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).


APPLICATIONS

  • Communications
  • Diversity radio systems
  • Multimode digital receivers
  • GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
  • Smart antenna systems
  • Battery-powered instruments
  • Handheld scope meters
  • Portable medical imaging
  • Ultrasound
  • Radar/LIDAR
  • PET/SPECT imaging

PRODUCT HIGHLIGHTS

1. The AD9609 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.
2. The sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.
3. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO and data output (D9 to D0) timing and offset adjustments, and voltage reference modes.
4. The AD9609 is packaged in a 32-lead RoHS compliant LFCSP that is pin compatible with the AD9629 12-bit ADC and the AD9649 14-bit ADC, enabling a simple migration path between 10-bit and 14-bit converters sampling from 20 MSPS to 80 MSPS.

Part Models 8
1ku List Price Starting From $4.63

close icon
Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
AD9609BCPZ-20
  • HTML
  • HTML
AD9609BCPZ-40
  • HTML
  • HTML
AD9609BCPZ-65
  • HTML
  • HTML
AD9609BCPZ-80
  • HTML
  • HTML
AD9609BCPZRL7-20
  • HTML
  • HTML
AD9609BCPZRL7-40
  • HTML
  • HTML
AD9609BCPZRL7-65
  • HTML
  • HTML
AD9609BCPZRL7-80
  • HTML
  • HTML

Filter by Model

reset

Reset Filters

Part Models

Product Lifecycle

PCN

Feb 1, 2024

- 24_0009

Qualification of alternative Wafer Fab for TSMC 0.18um Mixed Signal CMOS Process

AD9609BCPZ-20

PRODUCTION

AD9609BCPZ-40

PRODUCTION

AD9609BCPZ-65

PRODUCTION

AD9609BCPZ-80

PRODUCTION

AD9609BCPZRL7-20

PRODUCTION

AD9609BCPZRL7-40

PRODUCTION

AD9609BCPZRL7-65

PRODUCTION

AD9609BCPZRL7-80

PRODUCTION

Mar 13, 2017

- 17_0035

Power Down Sequence and DRVDD Voltage Restriction for AD9649, AD9629 and AD9609.

AD9609BCPZ-20

PRODUCTION

AD9609BCPZ-40

PRODUCTION

AD9609BCPZ-65

PRODUCTION

AD9609BCPZ-80

PRODUCTION

AD9609BCPZRL7-20

PRODUCTION

AD9609BCPZRL7-40

PRODUCTION

AD9609BCPZRL7-65

PRODUCTION

AD9609BCPZRL7-80

PRODUCTION

Nov 10, 2014

- 14_0047

Conversion of 5x5mm body Size LFCSP Package Outlines from Punch to Sawn and Transfer of Assembly Site to Amkor Philippines.

AD9609BCPZ-20

PRODUCTION

AD9609BCPZ-40

PRODUCTION

AD9609BCPZ-65

PRODUCTION

AD9609BCPZ-80

PRODUCTION

AD9609BCPZRL7-20

PRODUCTION

AD9609BCPZRL7-40

PRODUCTION

AD9609BCPZRL7-65

PRODUCTION

AD9609BCPZRL7-80

PRODUCTION

Filter by Model

reset

Reset Filters

Part Models

Product Lifecycle

PCN

Feb 1, 2024

- 24_0009

arrow down

Qualification of alternative Wafer Fab for TSMC 0.18um Mixed Signal CMOS Process

AD9609BCPZ-20

PRODUCTION

AD9609BCPZ-40

PRODUCTION

AD9609BCPZ-65

PRODUCTION

AD9609BCPZ-80

PRODUCTION

AD9609BCPZRL7-20

PRODUCTION

AD9609BCPZRL7-40

PRODUCTION

AD9609BCPZRL7-65

PRODUCTION

AD9609BCPZRL7-80

PRODUCTION

Mar 13, 2017

- 17_0035

arrow down

Power Down Sequence and DRVDD Voltage Restriction for AD9649, AD9629 and AD9609.

AD9609BCPZ-20

PRODUCTION

AD9609BCPZ-40

PRODUCTION

AD9609BCPZ-65

PRODUCTION

AD9609BCPZ-80

PRODUCTION

AD9609BCPZRL7-20

PRODUCTION

AD9609BCPZRL7-40

PRODUCTION

AD9609BCPZRL7-65

PRODUCTION

AD9609BCPZRL7-80

PRODUCTION

Nov 10, 2014

- 14_0047

arrow down

Conversion of 5x5mm body Size LFCSP Package Outlines from Punch to Sawn and Transfer of Assembly Site to Amkor Philippines.

AD9609BCPZ-20

PRODUCTION

AD9609BCPZ-40

PRODUCTION

AD9609BCPZ-65

PRODUCTION

AD9609BCPZ-80

PRODUCTION

AD9609BCPZRL7-20

PRODUCTION

AD9609BCPZRL7-40

PRODUCTION

AD9609BCPZRL7-65

PRODUCTION

AD9609BCPZRL7-80

PRODUCTION

Software & Part Ecosystem

Software & Part Ecosystem

Can't find the software or driver you need?

Request a Driver/Software
Evaluation Kit

Evaluation Kits 2

reference details image

EVAL-AD9609

AD9609 Evaluation Board

zoom

EVAL-AD9609

AD9609 Evaluation Board

AD9609 Evaluation Board

Product Detail

This page contains evaluation board documentation and ordering information for evaluating the AD9609.

The AD9609-80EBZ is an evaluation board for the AD9609, single 10-bit ADC. This reference design provides all of the support circuitry to operate devices in their various modes and configurations, It is designed to interface directly with the HSC-ADC-EVALCZ data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device’s hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI controller software package is also compatible with this hardware and allows the user to access the SPI programmable features of the AD9609.

The AD9609 data sheet provides additional information related to device configuration and performance and should be consulted when using these tools. All documents and Visual Analog and SPI Controller are available at the High Speed ADC Evaluation Boards page. For additional information or questions, please email highspeed.converters@analog.com.

reference details image

HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

zoom

HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

FPGA-Based Data Capture Kit

Features and Benefits

  • 64kB FIFO Depth
  • Works with single and multi-channel ADCs
  • Use with VisualAnalog® software
  • Based on Virtex-4 FPGA
  • May require adaptor to interface with some ADC eval boards
  • Allows programming of SPI control Up to 644 MSPS SDR / 800MSPS DDR Encode Rates on each channel
  • DDR Encode Rates on each channel

Product Detail

The HSC-ADC-EVALCZ high speed converter evaluation platform uses an FPGA based buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The board is connected to the PC through a USB port and is used with VisualAnalog® to quickly evaluate the performance of high speed ADCs. The evaluation kit is easy to set up. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC.
Tools & Simulations

Tools & Simulations 5

Recently Viewed