Clock Generation and Distribution
Analog Devices offers ultralow jitter clock distribution and clock generation products for wireless infrastructure, instrumentation, broadband, ATE, and other applications demanding sub picosecond performance. ADI clock products are ideal for clocking high performance analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). ADI clock ICs integrate PLL cores, dividers, phase offset, skew adjust, and clock drivers in small chip scale packages.
Subcategories
Product Selection Table
Latest Resources
Application Notes
- AN-2072: AD9545 EEPROM Management (Rev. 0) PDF
- AN-501: Aperture Uncertainty and ADC System Performance (Rev. A) PDF
- AN-0983: Introduction to Zero-Delay Clock Timing Techniques PDF
- AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0) PDF
- AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0) PDF
Press Releases
Demo Board Schematic
Technical Articles
- 5G Technology Devices for an O-RAN Wireless Solution
- Integrated Hardened DSP on DAC/ADC ICs Improves Wideband Multichannel Systems
- Power-Up Phase Determinism Using Multichip Synchronization Features in Integrated Wideband DACs and ADCs
-
Open-Source LIDAR Prototyping Platform
Analog Dialogue
-
Phase-Locked Loop (PLL) Fundamentals
Analog Dialogue
Circuit Note
Design Tools
Solutions Bulletins & Brochures
Webcasts
- Spread the Word: This Is the Power of Silence
- RF Front End Design for the ADRV9002 Narrow/Wideband Transceiver
- Unified Communications Platform for Next Gen Conferencing products
- Multi-Channel System Improvements Using Hardened DSP in Digitizer ICs
- Explaining Phase Noise
Videos
- ADI X-Band Developer's Kit
- 16 Channel Tx/Rx S-Band Phased Array RADAR Platform
- Perfection of Translation Loop: Eliminating Spurious Signals
- 16Tx/16Rx L/S-Band Phased Array Radar & EW Prototyping Platform
- AD-FMCLIDAR1-EBZ: LIDAR Developmemt Platform by Analog Devices
Tutorials
Frequently Asked Questions
- How do harmonic spurs in the output spectrum affect jitter (random or deterministic)?
- Help! My PLL came unlocked over temperature.
- Do different divide ratios cause variations in jitter?
- How do I feed a single-ended signal into a differential input?
- Do divide ratios change the propagation delay?