AD9546
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AD9546

Dual DPLL Digitized Clock Synchronizer

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Info : RECOMMENDED FOR NEW DESIGNS tooltip
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Part Details
Part Models 2
1ku List Price Starting From $19.25
Features
  • Digitized clock transport subsystem
  • 9 independent UTS blocks (time stamp egress ports)
  • 2 independent IUTS blocks (time stamp ingress ports)
  • Dual DPLL synchronizes 1 Hz to 750 MHz physical layer clocks, providing frequency translation with jitter cleaning of noisy references
  • Complies with ITU-T G.8262 and Telcordia GR-253
  • Supports Telcordia GR-1244, ITU-T G.812, ITU-T G.813, ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2
  • Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppb (5 × 10−8)
  • Both DPLLs feature a 24-bit fractional divider with 24-bit programmable modulus
  • Programmable digital loop filter bandwidth: 0.0001 Hz to 1850 Hz
  • 2 independent, programmable auxiliary NCOs (1 Hz to 65,535 Hz, resolution < 1.37 pHz), suitable for IEEE 1588 Version 2 servo feedback in PTP applications
  • Automatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operation
  • Programmable priority-based reference switching with manual, automatic revertive, and automatic nonrevertive modes supported
  • 5 pairs of clock output pins with each pair useable as differential LVDS/HCSL/CML or as 2 single-ended outputs (1 Hz to 500 MHz)
  • 2 differential or 8 single-ended input references
  • Crosspoint mux interconnects reference inputs to PLLs
  • Supports embedded (modulated) input/output clock signals
  • Fast DPLL locking modes
  • Provides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the frequency stability and accuracy of a TCXO or OCXO
  • External EEPROM support for autonomous initialization
  • Single 1.8 V power supply operation with internal regulation
  • Built in temperature monitor and alarm and temperature compensation for enhanced zero delay performance
Additional Details
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The AD9546 incorporates digitized clocking technology that efficiently transports and distributes clock signals in systems. Digitized clocking allows the design of flexible and scalable clock transport systems with well controlled phase (time) alignment. These characteristics make the AD9546 a leading choice for the design of network equipment that must meet the synchronization requirements for IEEE® 1588 boundary clocks per ITU-T G.8273.2 Class D. Digitized clocking is also relevant in applications requiring the accurate transport of frequency and phase to multiple usage endpoints (for example, distributing synchronized system reference (SYSREF) clocks to an array of ADC channels).

The AD9546 supports existing and emerging International Telecommunications Union (ITU) standards for the delivery of frequency, phase, and time of day over service provider packet networks (ITU-T G.8262, ITU-T G.812, ITU-T G.813, ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2).

The 10 clock outputs of the AD9546 synchronize to any one of up to eight input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references, and the analog phase-locked loops (APLLs) provide frequency translation with low jitter output clocks. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail.

The AD9546 is available in a 48-lead LFCSP (7 mm × 7 mm) package and operates over the −40°C to +85°C temperature range.

Throughout this data sheet, a single function of a multifunction pin name may be referenced when only that function is relevant (for example, M5 for SDO/M5).

APPLICATIONS

  • 5G timing transport high precision synchronization
  • Global positioning system (GPS), precision time protocol (PTP) (IEEE 1588), and synchronous Ethernet (SyncE) jitter cleanup and synchronization
  • Optical transport networks (OTN), synchronous digital hierarchy (SDH), and macro and small cell base stations Small base station clocking (baseband and radio)
  • Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control
  • JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking
  • Carrier Ethernet
Part Models 2
1ku List Price Starting From $19.25

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Documentation

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Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
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Product Lifecycle

PCN

Aug 8, 2022

- 22_0065

Data Sheet Revision for AD9543/AD9545/AD9546

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Part Models

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PCN

Aug 8, 2022

- 22_0065

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Data Sheet Revision for AD9543/AD9545/AD9546

Software & Part Ecosystem

Software & Part Ecosystem

Evaluation Kit

Evaluation Kits 1

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EVAL-AD9546

AD9546 Evaluation Board

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EVAL-AD9546

AD9546 Evaluation Board

AD9546 Evaluation Board

Features and Benefits

  • Simple power connection using 6 V wall adapter and on-board LDO voltage regulators
  • Ten AC-coupled output SMA connectors, with output termination for HCSL
  • Two single ended AC-coupled reference inputs, usable also as a one differential AC-coupled reference input
  • One single ended AC-coupled reference input and 1 single ended DC-coupled reference input, configurable to create together a differential AC-coupled reference input
  • Pin programmable, power on ready configurability
  • Status LEDs
  • PC control using a USB connection
  • Microsoft Windows-based Evaluation Software with simple graphical user interface

Product Detail

The AD9546 Evaluation Board is a compact, easy-to-use platform for evaluating all features of the AD9546 multiple input, 10-Output, Dual Channel, Numeric Clock Synchronizer. The AD9546 supports existing and emerging International Telecommunications Union (ITU) standards for the delivery of frequency, phase, and time of day over service provider packet networks, including ITU-G.8262, ITU-T G.812, ITU-T G.813, ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2.

The 10 clock outputs of the AD9546 are synchronized to any one of up to four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail. The AD9546 system clock is provided by a 52 MHz crystal. Alternatively, an external clock signal may be provided at a SMA connector (relative components must be populated to enable this functionality).

Applications

  • 5G timing transport high precision synchronization
  • Global positioning system (GPS), PTP (IEEE 1588), and synchronous Ethernet (SyncE) jitter cleanup and synchronization
  • Optical transport networks (OTN), synchronous digital hierarchy (SDH), and macro and small cell base stations
  • Small base station clocking (baseband and radio)
  • Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control
  • JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking
  • Carrier Ethernet
Tools & Simulations

Tools & Simulations 1

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