Features and Benefits
- Dual DPLL synchronizes 2 kHz to 750 MHz physical layer clocks providing frequency translation with jitter cleaning of noisy references
- Complies with ITU-T G.8262 and Telcordia GR-253
- Supports Telcordia GR-1244, ITU-T G.812, G.813, G.823, G.824, G.825, and G.8273.2
- Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppb
- Both DPLLs feature a 24-bit fractional divider with 24-bit programmable modulus
- Programmable digital loop filter bandwidth: 10−4 Hz to 1850 Hz
- Two independent, programmable auxiliary NCOs (1 Hz to 65,535 Hz, resolution < 1.4 × 10−12 Hz), suitable for IEEE 1588
- Version 2 servo feedback in PTP applications
- Automatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operation
- Programmable priority-based reference switching with manual, automatic revertive, and automatic nonrevertive modes supported
- 5 pairs of clock output pins with each pair useable as differential LVDS/HCSL/CML or as 2 single-ended outputs (1 Hz to 500 MHz)
- 2 differential or 4 single-ended input references
- Crosspoint mux interconnects reference inputs to PLLs
- Supports embedded (modulated) input/output clock signals
- Fast DPLL locking modes
- Provides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the frequency stability and accuracy of a TCXO or OCXO
- External EEPROM support for autonomous initialization
- Single 1.8 V power supply operation with internal regulation
- Built in temperature monitor/alarm and temperature compensation for enhanced zero delay performance
The AD9543 supports existing and emerging ITU standards for the delivery of frequency, phase, and time of day over service provider packet networks.
The 10 clock outputs of the AD9543 are synchronized to any one of up to four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail.
The AD9543 is available in a 48-lead LFCSP (7 mm × 7 mm) package and operates over the −40°C to +85°C temperature range.
Note that throughout this data sheet, multifunction pins, such as SDO/M5, are referred to either by the entire pin name or by a single function of the pin, for example, M5, when only that function is relevant.
- PTP (IEEE 1588), and SyncE jitter cleanup and synchronization
- Optical transport networks (OTN), SDH, and macro and small cell base stations
- OTN mapping/demapping with jitter cleaning
- Small base station clocking, including baseband and radio
- Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control
- JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking
- Cable infrastructures
- Carrier Ethernet
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
The AD9543 evaluation board is a compact, easy-to-use platform for evaluating all features of the AD9543 dual digital PLL and 1 PPS synchronizer. The AD9543 provides high-precision, multi-output clock generator functions, along with two on-chip jitter cleaning digital PLL cores. PLL0 and PLL1 are optimized for high performance synchronous clocking applications such as IEEE 1588 Version 2, Synchronous Ethernet, OTN, and next generation wireless baseband protocols. The PLLs are fully configurable via serial port control as well as configurable via an external EEPROM for power on ready configurations.
The AD9543 can output up to 5 differential clock signals, plus two single-ended clocks driven by a mix of two high performance digital PLLs, plue two high-precision NCOs (numerically controlled oscillators). 12 total outputs and 4 reference inputs are accessible on the evaluation board.
The output differential transmission line pairs use 50Ω single ended characteristic impedance and are connected to standard edge launch SMA connectors. The AD9543 has a fully configurable power supply to allow the user to evaluate the AD9543 while being powered directly by a step down switching regulator or external LDOs. The AD9543 evaluation board uses RoHS-compliant FR-4 material. For convenience, detailed information from the AD9543 data sheet has been included here. Use this user guide in conjunction with the datasheet that has been provided by ADI.
Features & Benefits
- Simple power connection using 6V wall adapter and on-board LDO voltage regulators.
- 10 ac-coupled single-ended (differential signal recombined via a balun) output SMA connectors, with user-configurable output termination for HCSL, CML, or LVDS-compatible (default).
- 4 configurable reference inputs, selectable between a single ended to differential reference input SMA connector.
- 1 ac-coupled single-ended input SMA connector for system clock.
- Pin programmable, power on ready configurability.
- Status LEDs.
- USB connection to PC.
- Microsoft Windows-based evaluation software with simple graphical user interface via an ACE plug-in module
Documentation & Resources
Tools & Simulations
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.