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特性
- Integrated 1 Tx × 2 Rx RF transceiver
- Operating frequency range of 70 MHz to 6000 MHz
- Transmitter and wideband receiver signal bandwidth from 12 kHzto 40 MHz
- Narrowband receiver signal bandwidth from 12 kHz to 2 MHz
- 2 fully integrated, fractional-N, RF synthesizers
- 2 fully integrated, fractional-N, RF PLLs to control external VCO banks
- Supports external LO
- LVDS and CMOS synchronous serial data interface options
- Low power monitor and sleep modes
- Fully integrated DPD for narrowband waveforms
- User-programmable ARM core with 928 kB memory
- Interfaces include 2× UART, 2× I2S, I2C, QSPI, SPI, JTAG
- Library of hardware accelerators
- Fully programmable via a 4-wire SPI
- Package: 196-ball, 10 mm × 10 mm, CSP_BGA
The ADRV9104 is a highly integrated RF transceiver with an integrated application processor that has a single transmitter, dual receivers, integrated synthesizers, and digital signal processing functions. Its high performance, highly linear, high dynamic range transceiver designed for the lowest power consumption to support portable, and battery powered equipment. The ADRV9104 operates from 70 MHz to 6000 MHz and covers the UHF, VHF (from 70MHz), industrial, scientific, and medical (ISM) bands, and cellular frequency bands in narrow-band (kHz) and wideband operation up to 40 MHz. The ADRV9104 is capable of both TDD and uncalibrated FDD operation.
The transceiver consists of two direct conversion signal paths with state-of-the-art noise figure, dynamic range and linearity. Dedicated Narrow Band Receiver path can support up to 2MHz of RF signal BW. Dedicated Wide Band Receiver path can support up to 40MHz of RF signal BW. Each complete receiver and transmitter subsystem includes dc offset correction (Rx only), quadrature error correction (QEC), and programmable digital filters, which eliminate the need for these functions in the digital baseband. In addition, several auxiliary functions, such as auxiliary analog-to-digital converters (ADCs), auxiliary digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs), are integrated to provide additional monitoring and control capability.
The transmitter has internal modulator functions that can support modulation schemes for typical Land Mobile Radio (LMR) standards, such as Analog FM, Digital Mobile Radio (DMR), P25. The modulator integrates the symbol mapping, interpolation and pulse shaping functions which allow the basedband processor to send the 2bit symbols to ADRV9014 transmitter for modulation.
The fully integrated phase-locked loops (PLLs) provide high performance, low power, fractional-N frequency synthesis for the transmitter, receiver, and clock sections. Careful design and layout techniques provide the isolation required in high performance personal radio applications.
All voltage-controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count. Integrated synthesizer is capable to interface with external Voltage Controlled Oscillator (VCO) to improve overall phase noise performance. The local oscillators (LOs) have flexible configuration options and include fast lock modes.
The fully integrated phase-locked loops (PLLs) with the necessary external VCO interface are capable of operating with banks of external VCOs to provide ultra low noise LOs for the transmitter and receivers.
The transceiver includes low power sleep and monitor modes to save power and extend the battery life of portable devices while monitoring communications.
The fully integrated, low power digital predistortion (DPD) is optimized for narrow-band TDD signals and enables linearization of high efficiency power amplifiers.
The ADRV9104 hosts a second processor, Processor Subsystem 2 (PS2), for users application specific programming. The ARM M4 has 928kB of useable memory, hardware accelerators, peripheral interfaces and runs up to 200MHz. This application processor can be used to implement modem like features on the transceiver customized to individual use cases.
The ADRV9104 core can be powered directly from 1.0 V and 1.8 V regulators and is controlled via a standard 4-wire serial port.
High data rate and low data rate interfaces are supported using configurable CMOS or low voltage differential signaling (LVDS) serial synchronous interface (SSI) choice. The ADRV9104 is packaged in a 10 mm × 10 mm, 0.65 pitch 196-ball chip scale package ball grid array (CSP_BGA).
Applications
- Land Mobile Radios
- Mobile Satellite and Satellite IoT
- Wireless microphones
- Mission critical communications systems
- Smart Meters
- Factory Automation
提问
在下面提交您的问题,我们将从 ADI 的知识库中给出最佳答案:
您可以在其他地方找到帮助
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产品技术资料帮助
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参考资料
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产品型号 | 引脚/封装图-中文版 | 文档 | CAD 符号,脚注和 3D模型 |
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ADRV9104BBCZ | CHIP SCALE BGA |
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ADRV9104BBCZ-REEL | CHIP SCALE BGA |
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- ADRV9104BBCZ
- 引脚/封装图-中文版
- CHIP SCALE BGA
- 文档
- HTML Material Declaration
- HTML Reliablity Data
- CAD 符号,脚注和 3D模型
- Ultra Librarian
- SamacSys
- ADRV9104BBCZ-REEL
- 引脚/封装图-中文版
- CHIP SCALE BGA
- 文档
- HTML Material Declaration
- HTML Reliablity Data
- CAD 符号,脚注和 3D模型
- Ultra Librarian
- SamacSys