ADH835S

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Aerospace, SiGe, BiCMOS, MMIC, PLL+VCO, 33 MHz to 4100 MHz

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概述

Wide band: 33 MHz – 4100 MHz
Maximum Phase Detector Rate: 100 MHz
PLL FOM:
- -230 dBc/Hz in Integer Mode
- -227 dBc/Hz in Fractional Mode
< 160 fs integrated RMS Jitter (1 kHz to 100 MHz)
Figure of Merit (FOM): -226 dBc/Hz

low noise floor: -165 dBc/Hz
2 Differential RF or 4 Single-Ended Outputs
External LO Input
32-Lead Hermetic SMT Package
Screened in accordance with MIL-PRF-38535, Class Level S

The ADH835S is a low noise, wide band, Fractional-N PLL that features an integrated VCO with a fundamental frequency of 2020 MHz to 4100 MHz, and an integrated VCO Output Divider (divide by 2/4/6/.../60/62) that together enable the ADH835S to generate frequencies from 33 MHz to 4100 MHz. Integrated Phase Detector (PD) and a delta sigma modulator capable of operating at up to 100 MHz enable wider loop-bandwidths, faster frequency changes along with excellent spectral performance. Two independent RF outputs, with independent gain control, enable the ADH835S to distribute identical frequency and phase signals to multiple destinations, at optimal signal levels tailored to each output. An external VCO input allows the ADH835S to lock external VCOs and enables cascaded LO architectures for MIMO radio applications. Two separate Charge Pump (CP) outputs enable separate loop filters optimized for both integrated and external VCOs, and seamless switching between integrated or external VCOs during operation. Programmable RF output phase feature can further phase adjust and synchronize multiple ADH835S enabling scalable MIMO and beam-forming radio architectures. Additional features include configurable output mute function that mutes RF outputs during frequency changes, Exact Frequency Mode that enables the ADH835S to generate fractional frequencies with 0 Hz frequency error, and the ability to synchronously change frequencies without changing the phase of the output signal.

Applications