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特性
- 双路DPLL可同步2 kHz至750 MHz物理层时钟，提供高噪声参考源的频率转换以及抖动净化功能
- 符合 ITU-T G.8262 和 Telcordia GR-253 标准
- 支持 Telcordia GR-1244、ITU-T G.812、G.813、G.823、G.824 和 G.825
- 连续频率监控和参考验证，频率偏差低至50 ppb
- 两个DPLL具有24位小数分频器和24位可编程模数
- 可编程数字环路滤波器带宽：10−4 Hz至1850 Hz
- 自动和手动保持和参考切换，提供零延迟、无中断或相位増建操作
- 基于优先级的可编程参考切换，支持手动、自动恢复和自动非恢复模式
- 5对时钟输出引脚，每对引脚均可用作差分LVDS/HCSL/CML或2路单端输出（1 Hz至500 MHz）
- 2 个差分或 4 个单端输入基准电压源
- 交叉点多路复用器将基准输入与 PLL 互连
- 支持嵌入式（调制）输入/输出时钟信号
- 快速DPLL锁定模式
- 提供内部功能，结合晶振或晶体振荡器的低相位噪声以及TCXO或OCXO的频率稳定性和精度
- 为自主初始化提供外部EEPROM支持
- 1.8 V单电源供电，具有内部调节特性
- 内置温度监控/报警和温度补偿，可增强零延迟性能
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AD9542的10个时钟输出与最多四个输入基准电压源之一同步。数字锁相环(DPLL)可减少与外部基准电压源相关的时序抖动。借助数字控制环路和保持电路，即使所有参考输入都失效，也能持续产生低抖动输出信号。
AD9542采用48引脚LFCSP (7 mm × 7 mm)封装，额定温度范围为−40°C至+85°C。
请注意，在整篇数据手册中，多功能引脚（如SDO/M5）由整个引脚名称或引脚的单个功能表示；例如M5即表示仅与此功能相关。
应用
- SyncE 抖动清除和同步
- 光传输网络(OTN)、SDH、宏和小型蜂窝基站
- 具有抖动净化功能的OTN映射/解映射
- 小型基站时钟，包括基带和无线电
- Stratum 2、Stratum 3e 和 Stratum 3 保持、抖动清除及相位瞬态控制
- JESD204B 支持模数转换器(ADC)和数模转换器(DAC)时钟
- 有线基础设施
- 载波以太网
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AD9542
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产品技术资料帮助
ADI公司所提供的资料均视为准确、可靠。但本公司不为用户在应用过程中侵犯任何专利权或第三方权利承担任何责任。技术指标的修改不再另行通知。本公司既没有含蓄的允许，也不允许借用ADI公司的专利或专利权的名义。本文出现的商标和注册商标所有权分别属于相应的公司。
参考资料
ADI 始终高度重视提供符合最高质量和可靠性水平的产品。我们通过将质量和可靠性检查纳入产品和工艺设计的各个范围以及制造过程来实现这一目标。出货产品的“零缺陷”始终是我们的目标。查看我们的质量和可靠性计划和认证以了解更多信息。
| 产品型号 | 引脚/封装图-中文版 | 文档 | CAD 符号，脚注和 3D模型 |
|---|---|---|---|
| AD9542BCPZ |
48-Lead LFCSP (7mm x 7mm x 0.75mm w/ EP)
|
|
|
| AD9542BCPZ-REEL7 |
48-Lead LFCSP (7mm x 7mm x 0.75mm w/ EP)
|
|
- AD9542BCPZ
- 引脚/封装图-中文版
-
48-Lead LFCSP (7mm x 7mm x 0.75mm w/ EP)
- 文档
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD 符号，脚注和 3D模型
-
Ultra Librarian
-
SamacSys
- AD9542BCPZ-REEL7
- 引脚/封装图-中文版
-
48-Lead LFCSP (7mm x 7mm x 0.75mm w/ EP)
- 文档
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD 符号，脚注和 3D模型
-
Ultra Librarian
-
SamacSys
根据型号筛选
产品型号
产品生命周期
PCN
10月 3, 2022
- 22_0207
AD9542 Data Sheet Specification Revision
AD9542BCPZ
量产
AD9542BCPZ-REEL7
量产
12月 13, 2018
- 18_0199
AD9542 Data Sheet Specification Changes
AD9542BCPZ
量产
AD9542BCPZ-REEL7
量产
根据型号筛选
产品型号
产品生命周期
PCN
10月 3, 2022
- 22_0207
AD9542 Data Sheet Specification Revision
12月 13, 2018
- 18_0199
AD9542 Data Sheet Specification Changes
软件和型号相关生态系统
评估套件 2
AD-JUPITER-EBZ
Software-Defined Radio
特性和优点
- RF/SDR
- ADRV9002 transceiver
- 2 x receiver, 2 x transmitter
- LO frequency range 30 MHz to 6 GHz
- 12 kHz to 40 MHz frequency bandwidth
- Sampling rate 12 kSPS to 61.44 MSPS
- External Device Clock Input
- External MCS Input
- RF Front-end
- Processing System
- Zynq UltraScale+ MPSoC XCZU3EG
- ARM Cortex-A53 1.5 GHz
- ARM Cortex-R5 500 MHz
- Mali-400 MP2 graphic processor
- Programmable logic 154 k
- DDR4 – 2 GB (x32)
- Boot source
- SD card 3.0
- Flash memory 128 MB
- User Interfaces
- USB 3.1 Gen 1 – Type C
- Upstream Facing Port (UFP)
- Downstream Facing Port (DFP)
- USB 2.0 compatible
- Ethernet 1000BASE-T RGMII
- Display Port v1.2 (2 lanes, 5.4 Gbps)
- SATA 3
- USB (micro) debug interface
- 16 GPIOs (3V3 LVCMOS)
- USB Type-C (power only)
- Power Sink 5V, 9V/3A
- USB Type-C (data)
- Power Sink 5V/3A
- Power Source 5V/0.9 A
- 802.3at POE compliant, 25.5 W Type2 (POE+)
产品详情
The AD-JUPITER-EBZ is a versatile software-defined platform based on Analog Devices ADRV9002 and Xilinx Zynq UltraScale+ MPSoC. The ADRV9002 is a new generation RF transceiver that has dual-channel transmitters, dual-channel receivers covering a frequency range of 30 MHz to 6 GHz. This device has a high-quality RF linearity performance and a set of advanced features like fast profiles switching, flexible power vs. performance configuration, fast frequency hopping, multi-chip synchronization, and digital pre-distortion (DPD) for narrow and wide band waveform.
The evaluation platform includes XCZU3EG processing device that has a wide range of interfaces, making the system capable of local processing or streaming to a remote host. It comes integrated in a self-contained ruggedized aluminum case, which gives flexibility in evaluating and prototyping across different environments.
APPLICATIONS
- Aerospace and Defense
- Communications
- Advanced Education
EVAL-AD9542
AD9542 Evaluation Board
特性和优点
- Simple power connection using 6V wall adapter and on-board LDO voltage regulators.
- 10 ac-coupled single-ended (differential signal recombined via a balun) output SMA connectors, with user-configurable output termination for HCSL, CML, or LVDS-compatible (default).
- 4 configurable reference inputs, selectable between a single ended to differential reference input SMA connector.
- 1 ac-coupled single-ended input SMA connector for system clock.
- Pin programmable, power on ready configurability.
- Status LEDs.
- USB connection to PC.
- Microsoft Windows-based evaluation software with simple graphical user interface via an ACE plug-in module
产品详情
The AD9542 evaluation board is a compact, easy-to-use platform for evaluating all features of the AD9542 dual digital PLL, synchronizer, and jitter cleaner. The AD9542 provides high-precision, multi-output clock generator functions, along with two on-chip jitter cleaning digital PLL cores. PLL0 and PLL1 are optimized for high performance synchronous clocking applications such as Synchronous Ethernet, OTN, and next generation wireless baseband protocols. The PLLs are fully configurable via serial port control as well as configurable via an external EEPROM for power on ready configurations.
The AD9542 can output up to 5 differential (or 10 single-ended) clock signals, plus two single-ended clocks driven by a mix of two high performance digital PLLs. 10 total outputs and 4 reference inputs are accessible on the evaluation board.
The output differential transmission line pairs use 50Ω single ended characteristic impedance and are connected to standard edge launch SMA connectors. The AD9542/PCBZ has a fully configurable power supply to allow the user to evaluate the AD9542 while being powered directly by a step down switching regulator or external LDOs. The AD9542 evaluation board uses RoHS-compliant FR-4 material. For convenience, detailed information from the AD9542 Datasheet has been included here. Use this user guide in conjunction with the datasheet that has been provided by ADI.
资料
WIKI
工具及仿真模型 1
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