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内容类型 |
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ADCLK914: Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer Data Sheet (Rev A, 10/2008) (pdf, 383 kB)
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产品数据手册 |
PDF
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AN-939: 利用AD9912的超奈奎斯特频率操作得到高RF输出信号
(pdf, 0)
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应用笔记 |
PDF
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AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal
(pdf, 221 kB)
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应用笔记 |
PDF
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AN-927: 确定杂散来源是DDS/DAC还是其他器件(例如开关电源)[中文版]
(pdf, 234 kB)
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应用笔记 |
PDF
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AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies)
(pdf, 170 kB)
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应用笔记 |
PDF
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AN-873: ADF4xxx系列PLL频率合成器的锁定检测
(pdf, 0)
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应用笔记 |
PDF
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AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers
(pdf, 207 kB)
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应用笔记 |
PDF
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AN-837: 基于DDS的时钟抖动性能与DAC重构滤波器性能的关系[中文版]
(pdf, 416 kB)
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应用笔记 |
PDF
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AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance
(pdf, 313 kB)
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应用笔记 |
PDF
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AN-823: 时钟应用中的直接数字频率合成器[中文版]
(pdf, 303 kB)
基于直接数字频率合成器的时钟系统的时间抖动
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应用笔记 |
PDF
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AN-823: Direct Digital Synthesizers in Clocking Applications Time
(pdf, 115 kB)
Jitter in Direct Digital Synthesizer-Based Clocking Systems
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应用笔记 |
PDF
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AN-769: 基于AD9540产生多时钟输出
(pdf, 130 kB)
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应用笔记 |
PDF
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AN-769: Generating Multiple Clock Outputs from the AD9540
(pdf, 0)
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应用笔记 |
PDF
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AN-756: 系统采样以及时钟相位噪声和抖动的影响[中文版]
(pdf, 808 kB)
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应用笔记 |
PDF
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AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter
(pdf, 291 kB)
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应用笔记 |
PDF
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AN-741: 鲜为人知的相位噪声特性
(pdf, 359 kB)
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应用笔记 |
PDF
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AN-501: 孔径不确定度与ADC系统性能[中文版]
(pdf, 227 kB)
在中频采样中的一个关键问题是孔径不确定度（抖动）
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应用笔记 |
PDF
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AN-501: Aperture Uncertainty and ADC System Performance
(pdf, 227 kB)
A Key Concern in IF Sampling is that of Aperture Uncertainty (Jitter)
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应用笔记 |
PDF
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MT-008: 将振荡器相位噪声转换为时间抖动
(pdf, 123 kB)
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技术指南 |
PDF
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UG-058: Setting Up the Evaluation Board for the ADCLK914
(pdf, 305 kB)
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用户指导 |
PDF
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Speedy A/Ds Demand Stable Clocks
by Jeff Keip, Analog Devices, Inc. (EE Times, 3/18/04)
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技术文章 |
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Design A Clock-Distribution Strategy With Confidence
by Demetrios Efstathiou
(Electronic Design, April 27, 2006)
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技术文章 |
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Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems
... Much of your system's performance depends on jitter specifications, so careful assessment is critical.
by Brad Brannon, Analog Devices (EDN, 12/7/2004)
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技术文章 |
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Clock Requirements For Data Converters
(Electronic Design, 2/2005)
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技术文章 |
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高速转换器时钟分配器件的端接[中文版]
(其它技术文章，2010年1月)
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《模拟对话》杂志 |
HTML
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模数转换器时钟优化：测试工程观点 [中文版]
(模拟对话, 第42卷，2008年2月)
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《模拟对话》杂志 |
HTML
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Analog-to-Digital Converter Clock Optimization: A Test Engineering Perspective
(pdf, 909 kB)
By Rob Reeder, Wayne Green, and Robert Shillito
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技术资料 |
PDF
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ADI推出数模转换器简化FPGA接口 (04 七月 2012)
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新闻发布 |
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ADI新款DAC可缩减电缆前端信号链尺寸 (15 二月 2012)
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新闻发布 |
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Expanding Family of Integrated Clock ICs
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概况 |
HTML
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数据转换器IC解决方案，第10卷 • 第7期
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解决方案通报 |
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RF IC解决方案通报，第10卷 • 第5期
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解决方案通报 |
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数模转换器IC 解决方案，第10卷 • 第1期
(pdf, 2912 kB)
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解决方案通报 |
PDF
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Why do I see reference spurs?
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常见问题解答 |
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Why is my phase noise shape changing when I change the PLL settings?
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常见问题解答 |
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Why doesn't the PLL make my reference input and the clock outputs line up?
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常见问题解答 |
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How do I optimize my PLL loop for the best phase noise and/or jitter?
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My loop is not locking. How do I debug this?
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How long does it take for the PLL to lock?
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Help! My PLL came unlocked over temperature.
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How do I choose between active and passive filter in PLL loop?
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Should I reference the passive filter to ground? or supply?
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常见问题解答 |
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How do the PLLs in the AD951x parts compare to other ADI PLLs?
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常见问题解答 |
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How does the clock clean-up function of the AD951x parts work?
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Why do I want to run a fast PFD frequency?
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常见问题解答 |
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Is it ok for me to connect the same power supply to both the charge pump and distribution power supply pins?
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常见问题解答 |
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Why can't I use a bandpass filter for my loop filter?
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常见问题解答 |
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Should I tie my loop filter to ground or PLL supply?
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常见问题解答 |
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The loop filter was working great until I changed the divide ratio in PLL. What happened?
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常见问题解答 |
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How do I use a VCO with a supply greater than 5V?
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常见问题解答 |
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What suppliers do you recommend for VCO/VCXOs?
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常见问题解答 |
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Do VCXOs have better phase noise and jitter performance than VCOs?
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常见问题解答 |
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How do I know which VCO will work best with the AD9510?
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常见问题解答 |
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Is there an advantage to running a higher VCO frequency than the output frequency?
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常见问题解答 |
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How do I determine if a VCO is good enough for my purpose?
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常见问题解答 |
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Is there any difference between the nature of an oscillator's phase noise and the phase noise from a clock chip?
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常见问题解答 |
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Do different divide ratios cause variations in jitter?
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常见问题解答 |
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I have a clocking scheme which requires several different division ratios simultaneously. I have a frequency plan, but I'm concerned about crosstalk. How much of a problem is this with your clock distribution chips?
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常见问题解答 |
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Do divide ratios change the propagation delay?
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常见问题解答 |
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I want to use the phase offset feature on the AD9510 dividers to generate two signals 90° out of phase. How accurate is the phase offset?
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常见问题解答 |
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On the AD951x clock ICs, does the phase offset (coarse delay) affect the jitter?
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常见问题解答 |
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Why doesn't the mini-divider support the divide ratio I want?
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常见问题解答 |
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I want to use the variable delay adjust, but the jitter is too high. What can I do?
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常见问题解答 |
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I changed the coarse phase adjust in the evaluation software, but nothing happened. What's going on?
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常见问题解答 |
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What is the difference between the coarse phase adjust and the fine delay adjust?
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常见问题解答 |
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What is the fine delay adjust which is available on certain LVDS/CMOS outputs?
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常见问题解答 |
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Does the fine delay adjust affect the jitter?
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常见问题解答 |
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Why is the fine delay adjust not available on all the outputs?
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常见问题解答 |
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Is there a way to cause Input/Output rising edges to be synchronous (zero delay) with the AD9510/11?
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常见问题解答 |
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Will the AD9510 work without a reference input signal?
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常见问题解答 |
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What are the best clock sources for a distribution-only design?
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常见问题解答 |
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I am not using the CLK1 input on the AD9510. Can I just leave it floating?
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常见问题解答 |
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How good does my input signal need to be?
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常见问题解答 |
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I turned off my reference but the Digital Lock Detect (DLD) still says I'm locked.
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常见问题解答 |
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Can I shift the threshold on clocks for single-ended inputs?
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常见问题解答 |
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The reference input is differential, but my reference is single-ended. Do I need to convert to differential to drive the AD9510?
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常见问题解答 |
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Will differential or single-ended inputs/outputs improve my jitter?
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常见问题解答 |
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Why should I use differential rather than single-ended?
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常见问题解答 |
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How do I feed a single-ended signal into a differential input?
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常见问题解答 |
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Why do you recommend AC coupling, rather than DC coupling, at the clock inputs?
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常见问题解答 |
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Are the ADI clock parts stand-alone clock sources or do I still have to buy a clock source to drive these parts?
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常见问题解答 |
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Which provides better performance - a clock source with sinewave output, or one with differential square wave outputs?
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常见问题解答 |
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On the AD9510, what is the relationship between clock output jitter and CLK1/CLK2 input slew rate?
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常见问题解答 |
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I'm trying to write to the part in single-byte mode, but I can't write anything. What am I doing wrong?
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常见问题解答 |
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Can I use the 951X clocks to drive a mixer (RF LO)?
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常见问题解答 |
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My applications are RF, not for clocking data converters. Can ADI's 951X ICs be used for RF applications?
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常见问题解答 |
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I have an input present at the clock input, but I'm not seeing an output?
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常见问题解答 |
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What happens to the AD9510/11 clock outputs if the Reference Input (REFIN) signal goes away?
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常见问题解答 |
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What clock frequency comes out of the AD9510 outputs when you first apply power to the device?
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常见问题解答 |
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Is it possible to impedance match a clock output if it is heavily loaded? (e.g. CL=100pF)
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I ran the AD9510 outputs at 1.4 GHz and they seem to work fine. Is there a problem running them at 1.4 GHz?
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常见问题解答 |
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What should I do with unused channels on the AD9510?
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常见问题解答 |
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Can I tri-state the AD9510 outputs?
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常见问题解答 |
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On the AD9510, how can I make sure that the duty cycle of output clocks stays within 40% to 60% duty cycle window?
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常见问题解答 |
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What is the effect of distributing harmonically related clocks (on chip or on board) in terms of jitter?
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常见问题解答 |
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Is there any reason to use a transformer on a differential clock output to obtain a "clean" single-ended clock output?
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常见问题解答 |
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What are some of the advantages/disadvantages of using LVPECL vs. LVDS outputs?
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常见问题解答 |
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Does the AD9510 support 2.5V PECL?
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How much bandwidth is required to process a PECL or LVDS output?
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If I use only one of the PECL differential outputs and the unused output is terminated in 50Ω, how will this affect the phase noise or jitter of the single-ended output?
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If I change the level of PECL output, does it affect the jitter?
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What is the best way to terminate LVPECL outputs to get lowest jitter?
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Is it okay to AC-couple PECL or LVDS outputs?
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What is the fan-out capability of the CMOS, LVDS, and LVPECL outputs?
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What is the proper termination (value and location) for outputs?
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Are outputs short-circuit protected?
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Are the CMOS drivers on the clock devices complementary?
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Some of the schematics in the AD951x data sheets show an LVPECL termination scheme which is different from the classic termination often seen (50 Ω to Vs - 2V, or the Thevenin equivalent thereof). How does this work, and how did you chose 200 Ω for the resistors? Can I use 100 ohms to improve the slew rate (or jitter)?
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常见问题解答 |
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I have pulled SYNCB low, but I still have output from a channel. Why?
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Why can I not get the same output amplitude or rise and fall times as stated in your datasheet?
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The AD9510 datasheet says to use an external pull-up resistor on the FUNCTION pin. Why do I need this and what range of resistors will work?
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May I use the AD9540 for spread spectrum clocking?
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常见问题解答 |
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Can I get two clock outputs from the AD9540?
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What's the advantage of a DDS-based clock generator?
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常见问题解答 |
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Why does the AD9540 require special filtering on its analog output. What are the requirements of this filter?
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I'm working with optical networks - SONET/SDH. Do ADI's clock chips support these applications?
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常见问题解答 |
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On my board, I can't get the same low jitter numbers that are shown in the datasheet. Am I doing something wrong?
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常见问题解答 |
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How do you determine the bandwidth over which phase noise is integrated to obtain jitter?
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Using the "ADC SNR method", what is the equivalent bandwidth for the jitter specification?
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How do harmonic spurs in the output spectrum affect jitter (random or deterministic)?
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When a jitter number is specified without an associated bandwidth, what bandwidth should be assumed?
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How do you specify jitter?
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How do I use the clock part for jitter clean-up?
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If jitter can be calculated from phase noise measurements, is it possible to calculate phase noise from jitter numbers?
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Does jitter vary with different clock frequencies? How about phase noise?
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I sure can't measure jitter with femtosecond resolution on my scope! How do you do it? How much confidence do you have in the jitter figures that you are quoting for these parts?
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常见问题解答 |
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Do you guarantee performance shown in ADIsimCLK?
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常见问题解答 |
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Who do I contact for technical support on ADIsimCLK?
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Should I use the minimum charge pump current settings in order to minimize power?
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常见问题解答 |
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Can I run CMOS outputs at 5V?
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常见问题解答 |
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Can I use different power supply voltages for the PECL output drivers?
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Is .01 uF sufficient for power supply pin bypass?
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My application has pretty tight power consumption requirements. I am very interested in the capabilities of the AD9510, but I don't need every feature. Is it possible to turn off the unused features and save power?
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常见问题解答 |
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Why don't you spec psrr and cmrr in the datasheet?
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How do I get two AD951x (with PLL) to synchronize to the same reference input edge?
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I really need >10 clock outputs. Can I use multiple chips together and still guarantee that all output clocks are synchronized to REFIN?
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How do I synchronize multiple clock devices?
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What happens if I run the part in an ambient environment which exceeds 85°C?
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How can I determine the die temperature of your device?
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My circuit board has both an analog GND and a digital GND. How should I connect the AD9510 pins labeled GND?
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What PCB layout recommendations do you have for the of the exposed paddle on the bottom side of the LFCSP package?
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RAQs index
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非常见问题解答 |
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术语表
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专业词汇表 |
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