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AD9278:  Octal LNA/VGA/AAF/ADC and CW I/Q Demodulator

Product Details

Product Status:Recommended for New Designs

The AD9278 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA); an anti-aliasing filter (AAF); a 12-bit, 10 MSPS to 65 MSPS analog-to-digital converter (ADC); and an I/Q demodulator with programmable phase rotation.

Each channel features a variable gain range of 45 dB, a fully differential signal path, an active input preamplifier termination, a maximum gain of up to 51 dB, and an ADC with a conversion rate of up to 65 MSPS. The channel is optimized for dynamic performance and low power in applications where a small package size is critical.

The LNA has a single-ended-to-differential gain that is selectable through the SPI. The LNA input noise is typically 1.3 nV/√Hz at a gain of 21.3 dB, and the combined input-referred noise of the entire channel is 1.3 nV/√Hz at maximum gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB LNA gain, the input SNR is roughly 88 dB. In CW Doppler mode, each LNA output drives an I/Q demodulator. Each demodulator has inde-pendently programmable phase rotation through the SPI with 16 phase settings.

The AD9278 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.

The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO±) for capturing data on the output and a frame clock (FCO±) trigger for signaling a new output byte are provided.

Powering down individual channels is supported to increase battery life for portable applications. A standby mode option allows quick power-up for power cycling. In CW Doppler opera-tion, the VGA, AAF, and ADC are powered down. The power of the TGC path scales with selectable ADC speed power modes.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudo-random patterns, and custom user-defined test patterns entered via the serial port interface.

Fabricated in an advanced BiCMOS process, the AD9278 is available in a 10 mm × 10 mm, RoHS compliant, 144-lead BGA. It is specified over the industrial temperature range of −40°C to +85°C.


8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator

  • Low power: 88 mW per channel, TGC mode, 40 MSPS;
    32 mW per channel, CW mode
  • 10 mm × 10 mm, 144-ball CSP-BGA
  • TGC channel input-referred noise: 1.3 nV/√Hz, max gain
  • Flexible power-down modes
  • Fast recovery from low power standby mode: <2 μs
  • Overload recovery: <10 ns

Low noise preamplifier (LNA)

  • Input-referred noise: 1.25 nV/√Hz, gain = 21.3 dB
  • Programmable gain: 15.6 dB/17.9 dB/21.3 dB
  • 0.1 dB compression: 1000 mV p-p/750 mV p-p/450 mV p-p
  • Dual-mode active input impedance matching
  • Bandwidth (BW): >50 MHz

Variable gain amplifier (VGA)

  • Attenuator range: −45 dB to 0 dB
  • Postamp gain (PGA): 21 dB/24 dB/27 dB/30 dB
  • Linear-in-dB gain control

Antialiasing filter (AAF)

  • Programmable second-order LPF from 8 MHz to 18 MHz
  • Programmable HPF

Analog-to-digital converter (ADC)

  • SNR: 70 dB, 12 bits up to 65 MSPS
  • Serial LVDS (ANSI-644, low power/reduced signal)

CW mode I/Q demodulator

  • Individual programmable phase rotation
  • Output dynamic range per channel: >158 dBc/√Hz
  • Output-referred SNR: 153 dBc/√Hz, 1 kHz offset, −3dBFS

Functional Block Diagram for AD9278

Evaluation Kits & Symbols & Footprints

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Product Recommendations & Reference Designs

Companion Products

Suggested Companion Products

Recommended Gain Control of VGA for the AD9278 Recommended Clock Drivers for the AD9278
  • For low jitter performance and integrated VCO, we recommend the AD9520-0 and AD9522-0.
  • For low jitter, low power, clock fanout buffers, we suggest the ADCLK846 or ADCLK946.
Recommended Driver Amplifiers for the AD9278
  • For I-to-V conversion and ADC driver in CW signal path, we recommend the ADA4896-2 or the ADA4897-2.
Recommended A/D Converter for the AD9278
  • For sampling the I and Q signals in analog beamforming applications, we recommend the AD7982.
Recommended Power Solutions

  • For selecting voltage regulator products, use ADIsimPower.

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Price, packaging, availability

Price Table Help

The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.

AD9278 Evaluation Board
Model Description Price RoHS View PCN/ PDN Check Inventory/
AD9278-50EBZ Status: Production Evaluation Board $250.00 Yes -

Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.

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