ADL5590

PRODUCTION

869 MHz TO 960 MHz Quadrature Modulator

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Overview

  • Operating frequencies: 869 MHz to 960 MHz
  • Output compression point P1dB: 16 dBm
  • Output third-order intercept point OIP3: 29 dBm at 900 MHz
  • Noise floor: −157 dBm/Hz
  • Sideband suppression:  <−50 dBc at 900 MHz
  • Baseband common-mode bias: 1.5 V
  • LO leakage:  −50 dBc at 900 MHz, POUT = 5 dBm
  • Single supply: 4.75 V to 5.25 V
  • Package: 36-lead, 6 mm × 6 mm LFCSP

This family of monolithic RF quadrature modulators is designed for use from 869 MHz to 960 MHz and from 1805 MHz to 1990 MHz. Excellent phase accuracy and amplitude balance enable high performance, direct RF modulation for communications systems.

The ADL5590 and ADL5591 can be used as direct RF modulators in digital communications systems such as those using the Global System for Mobile Communications (GSM) network. In addition, the devices are compatible with enhanced data rates for GSM evolution (EDGE).

This family is fabricated using an advanced silicon-germanium bipolar process from Analog Devices, Inc., and is available in a 36-lead, exposed pad LFCSP. The devices operate from −40°C to +85°C.

Applications

  • Wireless infrastructure
  • Optimized for GSM transmitters

ADL5590
869 MHz TO 960 MHz Quadrature Modulator
ADL5590-91 Functional Block Diagram ADL5590-5591 Pin Configuration
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Hardware Ecosystem

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Tools & Simulations

ADIsimRF

ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.

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ADIsimPLL™

ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.

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