Ultralow Power 16-Bit High Speed Signal Chain Solution for Portable Sampling Systems

The LTC2195 family of ultralow power, dual 16-bit, 25Msps to 125Msps analog-to-digital converters (ADCs) dissipate half the power of competing 16-bit solutions, extending battery run times in portable electronics. Despite consuming only ~1.5mW/Msps per channel, the LTC2195 does not shirk performance to save power, yielding a 76.8dB signal-to-noise ratio (SNR) and 90dB of spurious free dynamic range (SFDR) at baseband (0MHz–62.5MHz, the first Nyquist zone). Serial LVDS outputs reduce the number of data lines required for routing the ADC data while minimizing digital feedback.

Signal Path Design

The LTC2195 family is an ideal solution for applications that require 16-bit performance and ultralow power consumption to extend battery life. Portable medical imaging equipment is a perfect example. In many imaging applications the signal from the image sensor must be conditioned before being sampled by the ADC. For this task, it is important to choose a low noise, low power amplifier that matches the performance of the ADC, such as the LTC6406, which makes a good match for the LTC2195 family.

The LTC6406 is a fully differential amplifier with low noise (1.6nV/√Hz at the input) and high linearity (+44dBm OIP3 at 20MHz) in a small 3mm × 3mm QFN package. External resistors set the gain, giving the user maximum design flexibility. Low power consumption (59mW with a 3.3V supply) minimizes the effect on the system power budget. This amplifier also has a common mode voltage range that extends down to 0.5V meaning it can be paired seamlessly with the LTC2195, which has a nominal common mode voltage of 0.9V.

Typically the output of an image sensor is single-ended. This requires a single-ended to differential translation before being sampled by the ADC. If response to DC is also required, a transformer cannot be used. This situation mandates a low noise amplifier that is capable of doing single-ended to differential translation, like the LTC6406.

The amplifier must be followed by a filter to reduce the wideband noise of the amplifier and to isolate the output of the amplifier from the ADC inputs—the ADC inputs produce common mode glitches associated with the commutation of the sample caps. A filter helps attenuate these glitches, protecting the amplifier. A high order filter is not required, since the noise of the amplifier is fairly low. With a corner frequency of 12MHz, the filter used here is adequate—it does not degrade the performance of the ADC.

The final filter should be designed to reduce only the wideband noise of the amplifier, not as a selectivity filter with a steep transition band. A steep transition band in the filter increases insertion loss and degrades the OIP3 of the amplifier, which leads to distortion of the signal from the image sensor. The circuit shown in Figure 1 accomplishes this goal.

Figure 1. Imaging application.

Results

Figure 2 shows the performance of this circuit. The results show that the linearity of the amplifier does not degrade the SFDR of the ADC at low input frequencies. The SNR also remains unchanged at 76.5dB. The LTC6406 does not degrade the SNR or the SFDR of the LTC2195 when using it at unity gain.

Figure 2. FFT results of circuit in Figure 1 with FS = 125Msps FIN = 1MHz.

Modifications

For this design there are some trade-offs that can be made to change the performance of the system. First, the gain can change by increasing the feedback resistors, or decreasing the source resistors. Typically the source resistors are set by the output impedance of the sensor itself. The feedback resistors are then used to modify the gain of the amplifier. The LTC6406 can be used to produce attenuation or gain depending on the output of the image sensor. As the gain of the amplifier increases, the amount of compensation capacitance required to stabilize the amplifier decreases. In this unity gain application 1.8pF is enough to produce good results. If the amplifier is used to attenuate the signal, more capacitance is required.

The low order, low pass filter in Figure 1 attenuates the wideband noise of the amplifier with a cutoff frequency of 12MHz. This cutoff frequency can be increased by decreasing the value of the final capacitors. Because the amplifier cannot drive a low impedance, and the ADC wants to see a low impendence at its analog inputs the impendence of the filter has been optimized to satisfy both the amplifier and the ADC. If a higher order filter is required, it should be located prior to the final drive amplifier, and more gain should be used in the amplifier stage to accommodate for the insertion loss in the filter. Some filtering is required between the final amplifier and the ADC. Even a simple RC low pass filter is better than driving the ADC directly into the amplifier.

About the LTC2195

The LTC2195 is a 16-bit 125Msps, simultaneous sampling, dual ADC operating from a single 1.8V supply. This circuit can be easily applied to the 14- or 12-bit members of the family or to converters that sample at much lower sample rates. The LTC2195 family also contains dual and single channel ADCs with parallel outputs. The LTC2185, 2-channel ADC and the LTC2165 single channel ADC have the same excellent 16-bit performance and low power as the LTC2195, but with parallel outputs that can simplify the FPGA code required to collect data. These flexible ADCs include the choice of CMOS, DDR CMOS or DDR LVDS outputs with programmable digital output timing, programmable LVDS output current and optional LVDS output termination. The LTC2185 and LTC2165 also have the popular randomizer and alternate bit polarity features that help to reduce digital feedback. More information about alternate bit polarity mode and digital feedback can be found in the video “Reduce Digital Feedback in High Speed Data Conversion Systems - LTC2261” at www.analog.com. There are also pin-compatible 14- and 12-bit versions of the dual LTC2185 that also provide excellent performance, and extremely low power consumption for high speed ADCs. The complete family can be seen in Table 1.

Table 1. The new generation of ultralow power 16-bit ADCs
25Msps 40Msps 65Msps 80Msps 105Msps 125Msps
Single Channel 7 × 7 QFN 1.8V Single ADCs, Parallel Outputs 2160 2161 2162 2163 2164 2165
Dual Channel
9 × 9 QFN 1.8V Dual ADCs Parallel Outputs 2180 2181 2182 2183 2184 2185
7 × 8 QFN 1.8V Dual ADCs, Serial LVDS Outputs 2190 2191 2192 2193 2194 2195
Power (mW/Ch) 40 60 80 100 155 185

Conclusion

The LTC2195 is the perfect ADC for power-conscious, high resolution sensor applications, while the LTC6406 is a good match as a driver amplifier—it does not compromise the performance of the LTC2195 and its power requirements are also low. Data sheet performance of the ADC can be easily achieved by using a relatively low order filter to reduce the wideband noise of the amplifier. The pairing of the LTC2195 and the LTC6406 is the ideal combination for any portable image sensor application, combining excellent performance with low power consumption. For more information about the LTC2195 family and the LTC6406 visit www.analog.com.

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Clarence Mayott

Clarence Mayott is a mixed signal application section leader with over 10 years of experience at Linear Technology.

Beginning with the DC1151, a demo board for the LTC2246H, Clarence has designed nearly all of the high speed ADC demo boards for Linear Technology. These boards have been used for evaluation purposes in a wide range of applications. He designed demo boards with complete signal chains combining amplifiers and ADC combinations to help the end customer evaluate systems more easily. He also designed companion boards, including clock and signal source boards, to help facilitate the evaluation of high speed ADC demo boards. Clarence manages the continued development of PScope, the software used for various pipeline and SAR ADCs.

His expertise in design and layout of demo boards allows him to instruct customers on how to implement high speed ADCs into their own designs. He has worked on many technical areas, including medical, automotive and communications. His experience allows him to see schematic errors, minute layout errors, and other design flaws in designs.

With the release of the LTC2000, Clarence has expanded his knowledge base to include high speed DACs and waveform generation in addition to high speed ADCs. As an application section leader he oversees the continued development of LTDACGen a new software tool for generating complex waveforms for high speed DACs.

He has given technical trainings both within Linear Technology and to potential customers describing how to implement proper signal chains from the antenna through the FPGA.

He received an M.S. in Electrical Engineering from Santa Clara University and a B.S. degree in Electrical Engineering from California State University Polytechnic San Luis Obispo.

Clarence Mayott

Clarence Mayott

Clarence Mayott は、ミックスド・シグナル・アプリケーション部門のリーダーです。

Linear Technology において 10 年以上の業務経験を持ちます。お客様によるシステム評価を容易化するために、ADC とドライバ・アンプを使用するデモ用ボードの設計を行いました。そのボードでは、それらの IC を組み合わせて完全なシグナル・チェーンを構築しています。また、クロック/信号源用のボードをはじめとするコンパニオン・ボードの設計にも携わり、高速 ADC のデモ用ボードを使った評価を容易に行えるようにしました。さらに、パイプライン型/SAR 型 ADC 用のソフトウェア「PScope」の開発も主導してきました。

Clarence は、「LTC2000」のリリースに伴い、高速 ADC に加えて、高速 D/A コンバータ(DAC)や波形生成にまで知識の幅を広げました。アプリケーション部門のリーダーとして、新たなソフトウェア・ツール「LTDACGen」の開発も継続して監督しています。これは、高速 DAC 向けに複雑な波形を生成するためのツールです。

Clarence は、サンタクララ大学で電気工学の修士号、カリフォルニア州立ポリテクニック大学で電気工学の学士号を取得しています。