要約
When current source/sink digital-to-analog converters (IDACs) drive the loads, the difference between the channel supply voltage (PVDD) and the output load voltage is dropped across the load. This leads to on-chip power dissipation and therefore can result in excessive die temperatures that can affect the reliability and also reduce overall system efficiency. This article describes a simple method of dynamic power control as a means of alleviating this concern, while simultaneously reducing the solution size using a DC-to-DC converter with Analog Devices’ latest single-inductor multiple-output (SIMO) technology. With the dynamic power control, the IDAC supply voltage is maintained at a certain minimum level to keep the IDAC channel operational for any given output current and load voltage, thereby minimizing the on-chip power dissipation.
Theory
Output Stage of IDAC
The simplified output stage of an IDAC is shown in Figure 1. Of note is the output PMOS (NMOS) driver stage for current sourcing (sinking). The source of the MOS stage is connected to the load, and hence the load voltage determines the functioning of the IDAC. The load voltage should be sufficiently low (or high for the current sink) to maintain the output device in saturation and therefore maintain a high output impedance to drive the load with an accurately defined current.
Thermal Constraints
Therefore, the output stage of an IDAC will drop any headroom, that is, the difference between the supply and the load voltage, while also sourcing the output current. This leads to power dissipation in the output stage, which raises the temperature of the device. The on-chip power dissipation is nothing but the product of the headroom voltage and the output current.
The power dissipation on-chip can increase the die's junction temperature beyond recommended operating limits and can be a major concern for systems with a large channel density or with higher ambient temperatures.
Considering an IDAC channel made to source a maximum output current of 300 mA to a 10 Ω load with an IDAC supply PVDD of 3.5 V, the corresponding load voltage VOUT becomes 3 V as shown in Figure 1. The headroom voltage is thus 0.5 V and the on-chip power dissipation is approximately 0.5 V × 300 mA = 0.15 W. If the IDAC channel is then made to source a current lower than full scale or the load impedance is reduced, the load voltage is reduced, and excess headroom is dropped across the output MOS stage, which manifests as on-chip heat dissipation.
The junction temperature of the device relates to the power dissipation as given in Equation 1.
where,
TJ is the junction temperature.
PDISS is the on-chip power dissipation.
θJA is the junction thermal resistance, typically provided in the data sheet.
TA is the ambient temperature.
Another way of looking at Equation 1 is to determine the maximum ambient temperature permissible for a device for a given amount of power dissipation, which can be given as in Equation 2.
In a 49-ball WLCSP package, the maximum junction temperature TJ(MAX) cannot exceed 115°C and the thermal impedance θJA for this package is 30°C/W. In the previous example, for a single IDAC channel dissipating PDISS of 0.15 W internally, the temperature rise is 0.15 W × 30°C/W = 4.5°C. The maximum safe ambient temperature is derated to 110.5°C.
In case of four channels in a single package, with each channel dissipating 0.15 W internally, the total power dissipated on-chip is 0.6 W. The temperature rise due to four channels is PDISS × θJA = 0.6 W × 30°C/W = 18°C. Therefore, the maximum safe ambient temperature is derated to only 97°C.
Owing to ever-increasing channel density requirements in optical communication systems of today, it starts to become apparent that a TA(MAX) of 97°C can be a concern in the end application. It is common to have multiple-channel current output DACs driving optical loads such as laser diodes, silicon optical amplifiers, and silicon photomultipliers on a single board or system. Additionally, a dense packing can mean a significant increase in system temperature.
Dynamic Power Control
The problem of excessive on-chip power dissipation is ameliorated using a dynamically varying PVDD supply voltage, also known as dynamic power control (DPC). DPC aims to provide the PVDD supply voltage just enough to keep the IDAC channel operational for any given output current and load voltage.
DPC can have different kinds of implementation. One such method is to sense the load voltage using an ADC and then a microcontroller calculates the required PVDD voltage. This supply voltage can then be set by another voltage or current source/ sink DAC or indeed, even another channel of the IDAC being used.
There are multiple ways by which a DAC can actuate a change in PVDD. Figure 2 and Figure 3 provide the use of a voltage or current output DAC to margin the output of a switched mode regulator with programmable output having a feedback (FB) node.
This article details a simple implementation of dynamic power control for an IDAC AD5770R using a precision analog microcontroller ADuCM410 as a host and a SIMO switching regulator MAX77655.
This solution can be implemented for other IDAC families with other switching regulators, both from ADI. The MAX77655 facilitates the control of its output voltage using an I2C bus and hence does not need a DAC as stated earlier.
Testing Dynamic Power Control
Figure 4 shows the complete system design used to demonstrate the benefits of dynamic power control. The SIMO regulator channels are used to power the individual PVDD supplies of the IDAC. The host microcontroller is used to control both the regulator output and the IDAC output currents. The IDAC has an internal diagnostic multiplexer to bring out the output currents and the load voltages of each channel. The inbuilt analog-to-digital converter (ADC) of the host controller is used to sense and digitize the multiplexed output of the IDAC.
The algorithm for DPC can take different forms, but can be broadly classified into two types: one for cases where the IDAC is driving a known impedance, while another for cases where the IDAC is driving an unknown or varying impedance.
For known impedances, the microcontroller can perform a calculation to get the minimum supply required and accordingly set the PVDD supply voltage.
For unknown impedances or more commonly, for loads that exhibit varying impedances with temperatures, the host controller can first sense the load voltage while the PVDD supply is sufficiently high. The controller then can bring down the PVDD supply to an optimum value, which is the sum of the load voltage and the minimum headroom voltage. This step can then be triggered for every IDAC channel code change, or at fixed intervals in time, whichever is deemed appropriate for the end application.
Whatever the approach, a key specification of note is the minimum headroom voltage specification of the IDAC. Any difference between the PVDD supply voltage and the load voltage is dropped across the IDAC output stage and contributes to on-chip heat dissipation.
Results
For demonstration purposes, the results for only one of the IDAC channels (IDAC5) with a full-scale current range of 100 mA are plotted in Figure 5, which is made to drive a 22 Ω load. It should be noted that the IDAC has a minimum (PVDD – AVEE) supply requirement of 2.5 V and a minimum headroom voltage of 0.275 V. These limits must be adhered to by the firmware code running on the host microcontroller.
The on-chip power dissipation is calculated by measuring the difference between the PVDD supply voltage and the load voltage. This is done for both cases—one with having DPC as well as one without. In case of results without DPC, the PVDD supply voltage is fixed at 2.5 V, with AVEE = 0 V.
The total system power consumption is also noted by measuring the current drawn from the 3.3 V supply input to the switching regulator and the AVDD pin of the IDAC. Figure 6 shows the total power consumed from the 3.3 V supply for the entire current range of 0 mA to 100 mA.
Figure 7 and Figure 8 indicate the ripple plots observed on the PVDD and IDAC channel pins. Since the IDACs are driven by switching regulator outputs directly as shown in Figure 4, some amount of ripple is to be expected depending on the AC power supply rejection ratio (PSRR) specification of the IDAC. AC PSRR is a measure of the rejection of the output current to AC changes in the power supplies applied to the DAC. Ripple can be further removed by optimizing the output capacitor of the SIMO and/or using a filter at the SIMO PMIC outputs if an application demands it. These plots were obtained by using an LC filter between the SIMO output and the IDAC supply pin. An inductor with low ESR is recommended to be used as the IDAC can source or sink large amounts of current.
Implementation
The hardware implementation can take different forms depending on the end application. Figure 11 shows two options, one with a unipolar supply comprising of only the MAX77655 (top) and another option for bipolar supplies with another DC-to-DC converter, the ADP5073 (bottom) added to provide the negative supply. In both cases, the microcontroller is not shown. As seen, both the options chosen for the solution are very compact, fitting into dimensions of 1.275" × 0.605" and 1.502" × 0.918", respectively. Both the options have not been evaluated, but are rather a demonstration of the compactness of the solution size. Results were obtained using discrete boards. Figure 9 and Figure 10 indicate 3D renderings of the purported solution.
Conclusion
In summary, the dynamic power control causes lesser on-chip power dissipation on a current output DAC, and brings down the total power consumed while not affecting the load operation in a detrimental way. The SIMO topology switching regulators make for an ideal solution to drive IDACs such as the AD5770R, while also being compact in terms of layout and power efficiency.