Introduction

The LTC1709-7 takes advantage of PolyPhase^™ switching techniques to reduce the number of input capacitors and the inductor size and to increase battery life. As CPU clock frequencies increase, the demand for core supply current also increases. Today’s 22A CPU core current requirements push single-stage switchers to the max. The PolyPhase switching designed into the LTC1709-7 allows lower cost, lower profile parts to be used and also improves transient response.

The LTC1709-7 is a dual, current mode, PolyPhase controller that drives two synchronous buck stages 180° out of phase. This small, SSOP-36 packaged controller integrates four high current MOSFET drivers, a differential amp for true output remote sensing, automatic current sharing circuitry, a power-good indicator and 5-bit mobile VID control. The LTC1709-7 also features Burst Mode operation and discontinuous conduction mode operation at light loads. The resulting power supply solution is highly efficient under any load conditions and occupies minimal board space.

1-Step, 2-Phase CPU Core Supply

Figure 1 shows a typical application circuit using LTC1709-7 for the CPU core supply. In a 1-step configuration, the CPU core voltage is stepped down directly from the wall adapter or battery. The input voltage can be between 7V and 24V. The output voltage is between 0.925V and 2V, as programmed by the 5-bit VID inputs. This supply will provide a maximum current of 22A to the CPU core. With only one IC, four SO-8 MOSFETs and two 1.8µH low profile, surface mount inductors, an efficiency of 83% is achieved for a 20V input and a 1.8V/22A output. Greater than 80% efficiency can be maintained throughout the load range between 4A and 22A. Because of the high input voltage, the reverse recovery losses in the body diodes of the bottom MOSFETs can be significant. Schottky diodes are required in parallel with the bottom MOSFETs to alleviate the reverse recovery problem. Because of the relative high switching loss at the maximum input voltage, a switching frequency of 200kHz was chosen.

Figure 2 shows the measured load transient waveform with a 20V input and 1.6V output. The load current changes between 0.2A and 22A with a slew rate of about 30A/µs. With only six low ESR SP caps (180µF/4V) on the output, the maximum output voltage variation during the load transients is less than 140mV_P-P. Note that the high-to-low load step response is slower than the low-to-high load step response because of the small steady-state duty cycle. Active voltage positioning is employed in this design to reduce the number of output capacitors (refer to Linear Technology Design Solutions 10 for more details on active voltage positioning). R9 and R6 provide the output voltage positioning with no loss of efficiency.

2-Step, 2-Phase CPU Core Supply

In the 1-step solution described previously, the input voltage for the CPU core supply can be as high as 24V. The resulting low duty cycle slows down the high-to-low load transient response, as shown in Figure 2, and increases current stress in the synchronous FETs. This increases the size and cost of the output capacitors and MOSFETs. High input voltage also increases the switching loss and power dissipation in the top MOSFET. To minimize the heat generated in the core supply, it is desirable for the CPU core supply to draw power from a low input voltage source such as the 5V system supply. Because the 5V supply is usually generated from a battery or wall adapter, this approach requires a total of two steps of power conversion.

A 5V input, 2-step CPU core supply design is almost identical to that shown in Figure 1. The only differences are the component changes shown in the table in Figure 1. As shown in Figure 3, the 2-step design improves the light-load efficiency by 20% and the full-load efficiency by 2% compared to the 1-step solution. The load transient response, as shown in Figure 4, is also improved. With two fewer SP caps at the output, the 2-step circuit achieves performance similar to that of the 1-step.

Because the CPU power can be greater than 40W, the output current rating of the 5V supply powering the LT1709-7 may exceed 15A. This will significantly increase the power loss, cost and size of the 5V system supply circuit. If the 3.3V and 5V system supplies are generated from a 2-phase LTC1876 circuit, the power imbalance of two step-down channels in the LTC1876 circuit decreases the effectiveness of the input ripple current cancellation. More high voltage capacitors (>25V) have to be used on the input side of the LTC1876 circuit. Refer to the LTC1876 data sheet for more information.

To achieve a better efficiency and lower overall cost for the LTC1876 circuit, which powers the LT1709-7, it may be desirable to draw the CPU core power from two different sources, 3.3V and 5V, as shown in Figure 5. By doing so, the design of the 3.3V and 5V supplies can be optimized to minimize the power loss for the LTC1876 circuit. In addition, the 2-input design further improves the light load efficiency because of lower switching loss on the 3.3V input channel. Since there is no input ripple current cancellation, however, the 2-input design requires larger filtering capacitors on both the 3.3V and 5V rails; the low-to-high load step response will be slower than the single 5V input design, as indicated in Figure 6, because the 3.3V input channel has less voltage to increase the inductor current. More information on the 2-input, 2-phase design can be found in Linear Technology Design Note 222.

Table 1 compares the performance of the different design approaches. Clearly, the 2-step design has the advantage over the 1-step design in terms of performance and size of the CPU supply. The 5V input, 2-step design has the best performance in the core supply.

The LTC1709-7 based, low voltage, high current mobile CPU power supply achieves high efficiency and small size simultaneously. The savings in the capacitors, inductors and heat sinks help minimize the cost of the overall power supply. The LTC1709-7 circuits presented in this article are suitable for powering the high speed mobile CPUs that demand large core supply currents. Compared to the 1-step solution, the 2-step design provides better core supply efficiency and requires smaller output inductors and capacitors.