ADP2164

The ADP2164 is a synchronous, step-down dc-to-dc regulator in a compact, 4 mm × 4 mm LFCSP package. The ADP2164 requires minimal external components to provide a high efficiency solution with integrated power switch, synchronous rectifier, and internal compensation. The input voltage range of the ADP2164 is 2.7 V to 6.5 V.

The ADP2164 evaluation board provides an easy way to evalu-ate the device. This user guide describes how to quickly set up the board to collect performance data.

Complete information about the ADP2164 is available in the ADP2164 data sheet, which should be consulted in conjunction with this user guide when using the evaluation board.

AD-FMCOMMS3-EBZ は、3G / 4G 基地局や試験装置アプリケーション、ソフトウェア無線など、RF アプリケーションを想定した高性能、高集積化 RF トランシーバー AD9361 をベースに開発された高速アナログ・モジュールです。そのプログラマビリティと広帯域により、幅広いトランシーバー・アプリケーションに最適です。RF フロント・エンドに柔軟なミックスド・シグナル・ベースバンド・セクションや内蔵の周波数シンセサイザを組み合わせ、プロセッサや FPGA との設定可能なデジタル・インターフェースを提供することにより、設計を簡素化します。AD9361は 70 MHz ～ 6 GHz の範囲で動作し、ほとんどの認可帯域と無認可帯域をカバーします。サンプル・レート、デジタル・フィルタ、デシメーションを変更することにより、200 kHz 未満から 56 MHz までのチャンネル帯域幅に対応します。すべて、AD9361 内でプログラム可能です。

AD-FMCOMMS3-EBZ は、AD-FMCOMMS2-EBZ よりも広いチューニング範囲で単一プラットフォームを使用したいソフトウェア開発者やシステム設計者に最適です。この基板は RF 性能だけを追求するものではなく、超広帯域フロント・エンドが大きな特長です。データシートの仕様は2.4 GHz で満たしますが、これは基板で対応できる RF チューニング範囲の全体ではありません。プラットフォームで対応する範囲全体（70 MHz ～ 6 GHz）の一般的な性能データは、基板の文書に記載されています。この基板は主にシステム調査を目的としており、ソフトウェア・チームからさまざまな波形を収集してからカスタム・ハードウェアを完成させるときに活躍します。設計者の目的は波形を確認することにあり、性能の最後の 1 dB または 1% EVM まで追求するわけではありません。性能重視のプラットフォームについては、 AD-FMCOMMS2-EBZ を参照してください。

The AD-FMCOMMS4-EBZ provides software developers and system architect with a single 1 x 1 transceiver platform that can be software-configured for wideband tuning as well as narrowband RF performance.

In the wideband configuration, the AD-FMCOMMS4-EBZ will operate over the full 70 MHz to 6 GHz tuning range of the AD9364, however, the RF performance expectations of this configuration must be tempered with the very wide band front end. It will meet the AD9364 datasheet specifications at 2.4 GHz, but does not over the entire RF tuning range that the board can support. Typical performance data for the platform’s entire tuning range is published within the board documentation. This configuration is primarily intended for system investigation and bringing up various waveforms from a software team before custom hardware is complete. The objective being for designers to see waveforms, but not being concerned about the last 1dB or 1% EVM of performance.

The AD-FMCOMMS4-EBZ can also be user-configured for optimum performance in the 2400 – 2500 MHz band. In this configuration it may exhibit diminished RF performance on tuned frequencies or programmed configurations, outside of this band. This configuration is primarily intended to provide RF engineers with the ability to connect the AD9364 to an RF test bench (Vector Signal Analyzer, Signal generator, etc.) and achieve its optimum performance. The AD-FMCOMMS4-EBZ is a high-speed 1 x 1 agile RF transceiver analog FMC module software-tunable over the 56 MHz to 6 GHz band.

The AD-FMCOMMS2-EBZ is a high-speed analog module designed to showcase the AD9361, a high performance, highly integrated RF transceiver intended for use in RF applications, such as 3G and 4G base station and test equipment applications, and software defined radios. Its programmability and wideband capability make it ideal for a broad range of transceiver applications. The device combines an RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor or FPGA. The AD9361 chip operates in the 70 MHz to 6 GHz range, covering most licensed and unlicensed bands. The AD-FMCOMMS2-EBZ board comes specifically tuned and optimized to 2.4 GHz and due to the limitations of the on-board discrete external components, it may exhibit diminished RF performance on some other programmed configurations. The chip supports channel bandwidths from less than 200 kHz to 56 MHz by changing sample rate, digital filters, and decimation, all programmable within the AD9361 itself.

The AD-FMCOMMS2-EBZ provides RF engineers the ability to connect the AD9361 to a RF testbench (Vector Signal Analyzer, Signal generator, etc) and measure performance. The external components (which can easily be swapped) on the AD-FMCOMMS2-EBZ have a narrower RF tuning range 2400 – 2500 MHz. It is expected that most engineers will change these external components (pin for pin replacements from various vendors are available) for their specific application/frequency of interest. Anyone interested in a wider tuning range board should look at the AD-FMCOMMS3-EBZ.

The ADSP-SC589 EZ-KIT Lite and EZ-Board^® are evaluation systems for the ADSP-SC58x family of SHARC^® processors. The ADSP-SC589 processor is based on the SHARC+^™ core dual processor with the arm^® Cortex-A5^™ processor core and is designed for a wide array of markets, from automotive and pro-audio to industrial-based applications that require high floating-point performance. The EZ-Board is shipped with all of the necessary hardware—you can start the evaluation immediately. The package contains the standalone evaluation board, CE-approved power supply, and USB cable. The EZ-KIT Lite^® version ships with an EZ-Kit license for CrossCore^® Embedded Studio (CCES) and the ICE-1000 emulator, while the EZ-Board version requires the customer to provide an ICE-1000 or ICE-2000 emulator. The EZ-Kit license gives the user a full, subscription based license to use CCES with only the ADSP-SC589 EZ-KIT Lite evaluation board.

Expansion Interface III connectors are provided for interfacing with additional extender boards to provide LCD, camera, video, and audio. Traditional mechanical switches for changing the board's factory setup have been removed in favor of I2C controlled software switches. The only remaining mechanical switches are the boot mode switch, JTAG configuration switches, and push buttons.

The evaluation board is designed to be used in conjunction with the CrossCore^® Embedded Studio (CCES) development tools to test capabilities of the ADSP-SC58x processors. The development environment aids advanced application code development and debug, such as:

• Create, compile, assemble, and link application programs written in C++, C, and assembly
• Load, run, step, halt, and set breakpoints in application programs
• Read and write data and program memory
• Read and write core and peripheral registers

The AD-FMCADC4-EBZ is a high speed 4-channel data acquisition board featuring two AD9680 dual channel ADC at 1000 MSPS and four ADA4961 low distortion, 3.2 GHz, RF DGA driving each converter. The FMC form factor supports the JESD204B high speed serial interface. All clocking and channel synchronization is support on-board using the AD9528 clock generator. This product is designed for sampling wide bandwidth analog signals up to the second Nyquist zone. The combination of wide input bandwidth, high sampling rate, and excellent linearity of the AD9680 is ideally suited for spectrum analyzers, data acquisition systems, and a wide assortment of military electronics applications, such as radar and jamming/anti-jamming measures.

The board meets most of the FMC specifications in terms of mechanical size, mounting hole locations, and more. Although this board does meet most of the FMC specifications, it’s not meant as a commercial off the shelf (COTS) board. If you want a commercial, ready to integrate product, please refer to one of the many FMC manufacturers and the FMC specification (ANSI/VITA 57.1).

This board is targeted to use the ADI reference designs that work with Xilinx development systems. ADI provides complete source (HDL and software) to re-create those projects (minus the IP provided by the FPGA vendors, which we use), but may not provide enough info to port this to your custom platform.

The design of the board is specifically tailored to synchronizing multiple AD-FMCADC4-EBZ boards together. For more information on synchronization please refer to A Test Method for Synchronizing Multiple GSPS Converters. The reference design includes the device data capture via the JESD204B serial interface and the SPI interface. The samples are written to the external DDR-DRAM. It allows programming the device and monitoring its internal registers via SPI.