CN0540

The circuit shown in Figure 1 is a data acquisition (DAQ) signal chain for an IEPE sensor consisting of a current source, level shifting and attenuation stage with a digital-to-analog converter (DAC), a third-order antialiasing filter, an analog-to-digital converter (ADC) driver, and a fully differential Σ-Δ ADC.

The programmable current source drives the piezoelectric accelerometer with constant current. The output current can be programmed by external resistors and is usually set between 2 mA and 20 mA, depending on the type of sensor and the cable.

The buffered and amplified output of the DAC, together with the level shifting op-amp, shifts the input signal close to a 2.5 V common-mode voltage (V_OCM) to balance the input of the anti-aliasing filter and that of the fully differential amplifier (FDA). The second input of the FDA rail is set to 2.5 V, ensuring input headroom requirements are met, and the output is a fully differential voltage optimized for driving the ADC.

The antialiasing filter sets the bandwidth of the signal chain to 54 kHz. Piezoelectric accelerometers have bandwidths as high as 20 kHz, but a wider bandwidth signal chain has been chosen with respect to phase delay, achieving better phase matching performance in 3-axis measurements. (Further bandwidth limiting occurs in the digital filter of the ADCs, however, the phase delay is known and deterministic.)

ICP/IEPE VIBRATION SENSOR

Any IEPE vibration sensor can be interfaced with this CN-0540 reference design because all the IEPE vibration sensors work using the same principle with different offset voltages, noise levels, bandwidths, and sensitivities. An IEPE output signal carries both ac and dc voltages, where the vibration dependent ac voltage is dc shifted to some voltage level between 7 V and 13 V. This dc level varies from sensor to sensor, and for any given sensor, it has a drift component with respect to time, temperature, and excitation current.

The IEPE sensor must be powered by a current source with a sufficiently high voltage range to fully cover the amplitude of the sensor. A typical excitation voltage of the IEPE sensors is 24 V.

The input of the signal chain can receive a signal amplitude of up to 10 V p-p with an offset voltage up to 13 V. The dc offset is removed by applying a dc offset correction signal, allowing operation to an arbitrarily low frequency.

Figure 2 shows an ICP accelerometer block diagram of a sensor powered by a constant current source and connected to a dc-coupled signal chain. The maximum bandwidth of the sensor is proportional to the excitation current and inversely proportional to cable capacitance. The maximum desired output voltage of the sensor and cable type must be taken into account when choosing the level of the constant current, which can be determined by using the following equation:

where:

f_MAX is the maximum frequency of the sensor in hertz.
I_C is the constant current in mA.
1 mA is the power requirement of the sensor.
C is cable capacitance in pF.
V is the maximum peak voltage output from the sensor in volts.

Note that in Equation 1, 1 mA is subtracted from the total current supplied to the sensor (I_C), where the approximate 1 mA is for powering the sensor itself and the rest of the current is for driving the cable. This number varies from sensor to sensor.

For example, this reference design was tested using an ICP accelerometer produced by PCB Piezotronics, Model 333B52 with a maximum peak output of 10 V, a 10 ft. cable length with a capacitance of 29 pF/ft., and an excitation current of 2.5 mA. Applying Equation 1, the maximum theoretical bandwidth of the sensor is 82.3 kHz. Neither the cable nor the chosen current level limit the performance of the sensor.

INPUT PROTECTION

Because IEPE sensors are typically connected to the DAQ system via long cables, and in an environment where many cables and other signal types are present, it is important to protect the DAQ system from any overvoltages that may occur due to operator miswiring or cable damage. The ADG5421F is an input protection switch that automatically detects overvoltage conditions and open circuits the sensor from the data acquisition signal path.

For the switches to be active, input signal levels from the sensor must be within the V_SS − V_T and V_DD + V_T range. Note that V_SS is the negative power supply pin, V_T is the voltage threshold, and V_DD is the positive power supply pin.

The ADG5421F also provides a fault flag (FF) that can be used as an interrupt into a controller to alert the operator that an input fault has occurred. In normal operation, the FF pin is pulled high. However, if either the S1 pin or the S2 pin exceeds 26 V or 0 V by V_T (0.7 V), the FF pin is pulled low to indicate a fault has occurred. If a fault is detected in the CN-0540, the sensor input and current source disconnects from the data acquisition system.

CONSTANT CURRENT SOURCE

Take care when designing the constant current source (CCS) and when considering noise performance. Low current noise is essential because current noise is converted to voltage noise when driving the input impedance of the signal chain.

Figure 3 depicts a 2-terminal current source with Resistors R_SET and R_OUT setting the output current to 4.5 mA and Capacitor C_SET limiting the bandwidth of the current noise. The internal 10 μA reference current source of the LT3092 holds a stable V_SET across R_SET. The V_SET is mirrored across R_OUT, which sets the output current according to Equation 2.

Note that the actual I_OUT current is 10 μA larger than the output current given by Equation 3 because of the internal reference current flowing from the SET terminal.

The data sheet recommends R_SET = 20 kΩ to set the voltage drop across R_SET to 200 mV, minimizing the effect of the offset voltage. (The offset voltage is more significant across a smaller V_SET.) The white current noise produced by a resistor is given by Equation 3.

where:

T is absolute temperature in Kelvin.
k is Boltzmann’s constant in (J/K).
R is resistance.

Because resistor current noise is proportional to the square root of the inverse of resistance, increasing the value of R_SET from the recommended 20 kΩ to 120 kΩ requires a proportional increase in R_OUT as well (keeping the output current at the same level), causing a drop in the overall noise current. A capacitor, C_SET, across R_SET is recommended to lower the current noise of R_SET and of the internal current reference of the LT3092. The C_SET capacitor bypasses the current noise emitting from the LT3092.

An LT spice simulation of the constant current source, as shown in Figure 3, was performed to optimize component values and placement dependency. A nonideal voltage source was modeled, providing 0.7 mV rms voltage noise and 224 nA rms of current noise in a 20 MHz bandwidth, simulating a Keysight E3631 bench power supply with two outputs connected in series, set to 26 V total.

Table 1 lists rms noise for various combinations of component values. The rms current noise was simulated for a bandwidth from 1 mHz to 100 kHz. CCOMP acts like a high-pass filter, passing the noise from the voltage source to the output. Further increasing R_SET and R_OUT helps in the current noise reduction, but it also causes a higher voltage drop over the resistors, reducing the allowable signal swing.

When using a long cable with a high level of inductance, stability may become an issue. For more information on compensating inductive loads, refer to the LT3092 data sheet.

To calculate the usable sensor excitation voltage provided by the current source, use the following equation:

where:

V_DD is the supply voltage of the constant current source.
LT3092_DROP is the dropout voltage over the IC itself (typically 1.2 V at load current up to 10 mA).
R_SET × 10 μA gives the dropout voltage over the resistor, which sets the output current level and a current from the internal 10 μA flows through the resistor.

In this case, the usable excitation voltage is 23.6 V.

VOLTAGE LEVEL SHIFTER

The voltage level shifter tolerates a sensor offset voltage up to 13 V, with a signal swing up to 10 V p-p, accommodating the majority of piezoelectric sensors on the market. An inverting voltage level shifter topology with an op-amp has been chosen, where a positive shifting voltage is required to bring the input voltage down to accommodate the FDA stage input requirements.

Figure 4 depicts an inverting voltage level shifter topology with an op-amp. Calculate the shifting voltage by the following equation:

The V_OUT voltage produced by the voltage shifter is set to be as close to V_OCM (2.5 V) as possible to balance the input of the FDA in the following stage. The R_F/R_IN ratio (the attenuation of the op-amp) must respect the following constraints:

• Supply voltage of the shifting op-amp: 5 V
• Range of the shifting voltage: 0 V to 5 V
• Stability of the op-amp
• Full-scale range of the ADC: ±4.096 V
• Input signal amplitude: 10 V p-p
• Input dc offset voltage: up to 13 V

An attenuation of 0.3 is a reasonable compromise, and a small gain in the following stage maximizes the input amplitude to the ADC and increases signal-to-noise ratio (SNR). Note that both the signal and noise at the output of the level shifter are amplified, so minimizing the output noise of the level shifter is critical.

A compromise has been made in CN0540 between input impedance and input noise, with an input noise level low enough and input resistance high enough to prevent introducing a measurement error. Piezoelectric sensors are generally low impedance output (hundreds of ohms) sensors and even a relatively low input impedance of the signal chain (tens of kΩ) introduces less than 1% of error. The final input impedance of R_IN = 50 kΩ has been chosen as a compromise.

Use the following equations to calculate the voltage noise of the level shifter block with a shorted input:

where:

k is Boltzmann’s constant.
T is the absolute temperature in Kelvin.
R is the resistance in ohms.

All the contributions, excluding R_IN, must be multiplied by the noise gain before squaring. The noise gain of an inverting op-amp configuration is the same as that of a noninverting configuration.

Use the following equation to calculate the inverting input op-amp noise contribution:

where NG is the noise gain of the circuit.

The single-pole RC filter at the voltage level shifter block limits the noise. Use the following equation, to calculate the rms value of noise produced by the voltage level shifter:

The noise contribution of the first stage is 20.8 μV rms, where the most significant noise contributor is the R_IN, a consequence of setting the input impedance high enough to minimize errors due to loading.

DC BIAS COMPENSATING TECHNIQUE

Each IEPE accelerometer has a certain dc bias voltage that must be removed because this voltage does not carry any useful information. If dc coupling is used in a signal chain, the input voltage can be dc shifted to null the dc bias voltage, such that the ADC acknowledges only the ac portion of the input voltage without any dc offset. Precise dc shifting is crucial for accuracy in dc measurements and for maximizing the dynamic range of measurements.

An exact shifting voltage can be discovered using the shifting voltage in Equation 5. Following this approach, numbers of measurements at different temperatures must be taken for each board and sensor separately, thereby ensuing accuracy of the measurements.

Other, more precise, reliable, and automated techniques have been used. A custom successive approximation algorithm has been employed in the CN0540. Because the standard successive approximation model is estimating the final position of an unknown voltage level using a DAC to ADC control loop, this custom successive approximation is trying to set a mean voltage at the input of the ADC as close to 0 as possible using the DAC to ADC loop. In other words, the main goal is to set both inputs of the FDA to the same voltage level, which is V_COM = 2.5 V.

Table 2 shows the process of input bias voltage compensation using the successive approximation algorithm. Because a 16-bit DAC has been chosen, there are 16 iterations. At the very beginning of the process, the DAC is set to a half-scale output. Every time the DAC is set to a new value, the mean voltage is measured. If the mean voltage is positive, a 1-bit weight is added to the current DAC output. Otherwise, a 1-bit weight is subtracted from the current DAC output. The process is inverted due to the input op-amp being in an inverting configuration.

Equation 11 shows the bit weights being added or subtracted. 2¹⁵ − 1 is the initial half-scale value followed by two ups and one down, meaning that the 14^th and 13^th bits are added and the 12^th bit is subtracted.

The piezoelectric sensor itself produces a significant amount of voltage noise caused by the internal structure of the sensor. Upon the sensor being powered, environmental noise is picked up by the sensor all the time, resulting in even more noise converted from mechanical environmental events into voltage noise. To extract only the dc bias voltage of the piezoelectric sensor, and to remove quite a significant amount of noise (which is either random or periodical), a lot of averaging is taking place in the dc bias compensating process.

LEVEL SHIFTING DAC

A 16-bit voltage output DAC (LTC2606) with 27 selectable I²C addresses has been chosen for the level shifting. The DAC has a 2.5 V reference. To achieve the full 0 V to 5 V shifting voltage range preset at the noninverting input of the shifting op-amp, and to lower the DAC output voltage noise, an external buffer has been added. The buffer has the Sallen-Key structure with a cutoff frequency of 100 Hz and a gain of 2. The LSB of the DAC with a gained output follows:

There are also other gains on the path from the DAC to the ADC input. One LSB change observed by the ADC input is gained by 6.93 as a product of all the gains, giving an equivalent LSB size as follows: 

where 2.667 is the gain of the FDA, and 1.3 is the gain of the shifting op-amp, which acts like a noninverting op-amp when a changing signal is brought to the noninverting input and the actual gain is 1 + (R_F/R_IN). The Equation 13 calculation gives the maximal theoretical dc error caused by shifting the sensor to the correct level.

Table 2 proves that one DAC LSB converted by the ADC is about 264 μV. Reviewing the last two ADC readings, the difference is only 1 LSB, resulting in 269 μV.

Figure 5 displays how the rms noise changes with only the input bias voltage applied to the input of the signal chain. Every time the input bias is changed, the DAC shifts the input to the correct level, ensuring a low offset error. The rms noise of the signal chain increases with the dc bias because the dc calibrator providing the dc bias produces more noise at higher voltage output levels.

As expected from Figure 5, the dynamic range responds to the increasing rms noise with the increasing input bias voltage in Figure 6.

Figure 7 displays the linearity of the system vs. the input bias voltage, using an input signal with a frequency of 1 kHz and an amplitude of 1 V p-p. Figure 7 shows that the input bias voltage has no significant impact on linearity and that the total harmonic distortion (THD) is stable.

Figure 8 displays the offset voltage error preset at the input of the ADC over temperature. The offset error was determined by running the input bias voltage compensation process over the temperature range with the same input voltage (10 V). The measurement at 25°C was set as 0 V of the offset error.

A voltage reference chip (ADR4540) with an output of 4.096 V was used, and the 2.5 V V_OCM was derived from it.

DAC BUFFER

The internal buffer of the DAC limits the voltage noise and must be filtered. The DAC output must also be amplified to provide 0 V to 5 V because the DAC uses a 2.5 V reference.

Figure 9 depicts the level shifting DAC with a gained output using a low-pass Sallen-key filter structure. The cutoff frequency of the filter has been set to a low value of approximately 100 Hz using the following formula:

Because a gain is applied to the Sallen-key filter topology, the stability of the filter must be considered. Otherwise, the buffer is likely to become an oscillator. Another factor, related to the stability, is the quality (Q) of a filter that must be considered for this block. By keeping the Q factor low enough (at less than 0.707), it ensures that the frequency response has no peaking at the cutoff frequency and that the roll offs have gentler slopes and begin significantly sooner than at the cutoff frequency. A low Q factor is suitable for this application, where high linearity over frequency is desired. Note that the structure becomes unstable whenever the Q factor becomes negative. Use the following equation to determine the Q factor is determined:

where k is the gain of the Sallen-key topology, as follows:

For the values in Figure 9, the cutoff is 147.6 Hz, k is 2, and Q is 0.125, where stability and smooth roll off are ensured.

A comparison showing noise performance between the DAC shifting block with and without a buffer was made. Note that the signal chain used for this measurement has 12.3 μV rms of noise and 108.2 dB of dynamic range with shorted inputs. The rms noise was measured at a 64 kHz bandwidth.

Table 3 shows how output voltage changes with the DAC code. The DAC output was gradually set from zero to quarter scale, half scale, and up to three-quarter scale. In the worst case scenario, the DAC shifting block noise contribution is only 1.3 μV rms.

ANTIALIASING FILTER AND FDA

The antialiasing filter and FDA use a differential multiple feedback low-pass structure with conversion from a single-ended to a differential signal. The cutoff frequency of the antialiasing filter has been set to 54 kHz, which is wider than the bandwidth of the majority of piezoelectric accelerometers. The filter provides a stopband rejection of −80 dB at 2.3 MHz.

The gain of this stage has been set to 2.667 to improve the SNR by boosting the input amplitude to more closely match the ±V_REF range at the input of the ADC. The wideband noise is also amplified by the FDA, but this degradation is not as large as the improvement due to signal gain because the antialiasing filter limits wideband noise.

ANALOG-TO-DIGITAL CONVERSION

The AD7768-1, a precision, 1-channel, 24-bit, Σ-Δ ADC has been chosen for its excellent dc to 204 kHz bandwidth precision, low power consumption, typical 108.5 dB dynamic range, and −120 dB THD.

Use Equation 17 to calculate the output data rate of the ADC:

where:

MCLK is master clock.
MCLK_DIV is a master clock divider factor.
FILTER_OSR is the oversampling ratio (OSR) of a selected digital filter.

The clock divider and the filter OSR are register settings and can be changed over the SPI bus. OSRs for finite impulse response (FIR) and SINC5 filters are strictly set in the register map of the AD7768-1. A user can set the SINC3 filter to their own preferable OSR and change the output data rate by writing a specific value into a 12-bit SINC3 decimation rate register using the following equation:

where ODR is the desired output data rate in Hz, and 2¹³ is the maximum possible value accepted by the SINC3 register. For example, the SINC3 register value for an output data rate of 4 Hz, with 16.384 MHz of MCLK, and a low power mode (MCLK/16) is 7999.

The default settings for this reference design are optimized for an ADC measurement bandwidth of 32 kHz, as follows:

• Power mode: low power mode
• MCLK divider: 16
• Filter type: FIR
• Filter decimation ratio: 32
• Input precharge buffers: enabled
• Reference buffers: precharge enabled
• VCM pin output: (AVDD1 − AVSS)/2
• Conversion length: 24 bits
• Conversion mode: continuous
• Checksum: no checksum
• Data read mode: continuous
• Status bit: disabled
• DRDY signal: enabled

Both buffers can be turned off when targeting a low power, demanding application. However, keeping the buffers on improves overall THD and SNR.

MEASURED PERFORMANCE OF THE SIGNAL CHAIN

This signal chain design targets medium to wider bandwidth vibration sensing, where higher harmonics and frequency content above 1 kHz is important. In the design, here is a necessary trade-off between the system bandwidth, linearity, and the achievable noise performance. Higher input impedance is chosen to maintain signal accuracy (linearity), which in this design sets a maximum noise performance limit. The signal bandwidth is also set wider so that the response of the system over higher frequencies is maintained. A lower noise solution can be achieved with a design that has a narrower bandwidth, thus removing more of the wideband noise.

The CN-0540 sets the analog input bandwidth to 54 kHz, but the actual signal bandwidth is determined by the ADC configuration settings.

Noise

Noise performance of the entire signal chain was measured in several different scenarios.

Table 5 details the typical noise performance of the signal chain, without any sensor connected, as well as when a 1 kΩ load resistor is added. The results with the 1 kΩ resistor connected at the input of the signal chain indicates that the constant current source impacts the noise performance. The current noise is transformed to voltage noise and multiplied by the resistance of the 1 kΩ resistor, causing an elevation of the system noise.

Figure 10 shows the typical FFT plot for the system with shorted inputs. Figure 11 shows the dynamic range of the dc-coupled solution with shorted input over temperature.

Sensor Noise Contributions

The usual aim of the designer of a data acquisition system is to capture the sensor output signal as accurately as possible. What this means in practice is that the performance of the system should be set by the sensor characteristics. The noise performance of the sensor is often one of the key limiting factors to the overall measurement system, understanding this helps to set the performance requirement of the design.

For this design, the target was to support sensors that provide vibration data at bandwidths greater than 1 kHz, which are used in data acquisition systems targeted at condition-based monitoring for predictive maintenance on rotating or reciprocating plant equipment.

Table 6 details the performance level and bandwidth of a small selection of vibration sensors. The main considerations in sensor selection tend to be bandwidth, range, noise spectral density (NSD), and power.

The ADXL1002 and ADXL1004 sensors are low power devices suitable for a range of vibration applications, where power and bandwidth are important. These accelerometers are suitable for continuous monitoring applications, such as Internet of Things (IoT) machine monitoring.

For the highest sensitivities and bandwidths, where low noise and sensitivity at higher frequencies is key, piezoelectric sensors are still the most appropriate sensors to use. Because of the wide bandwidth and low noise capabilities of the AD7768-1, this signal chain is adapted to match the performance level of typical sensors in that wider bandwidth range beyond 10 kHz.

In the case of CN-0540, the system bandwidth is set to 54 kHz, and the signal chain noise performance is aimed at sensors that can achieve >100 dB dynamic range over that bandwidth. For example, Piezotronics PCB Model 621B40 accelerometer, which achieves almost 105 dB at 30 kHz.

This circuit can be adapted for sensors with higher dynamic range and narrower bandwidths by scaling the resistor values and gains of the stages and by utilizing the higher oversampling modes of the AD7768-1. A complete analysis is beyond the scope of this document, but more information on the trade-off between dynamic range and bandwidth using oversampling can be found in the AD7768-1 data sheet.

Linearity

The linearity of a sensor measurement system is important to give confidence that the measurement results do not vary due to variations in the output of the sensor. The measurement system accuracy should not vary as the output bias voltage or the signal amplitude of the sensor vary. Ideally, this accuracy should also be maintained as the temperature of the measurement system changes.

The CN-0540 was designed to be as linear as possible and to maintain that linearity over temperature so that less calibration of the measurement signal chain is required. The nonlinearity of the system to dc input voltage changes is reported as INL error. The nonlinearity of the system to sinewave inputs is reported as THD error.

The data in Figure 12 and Figure 13 show that the dc linearity (INL) is within ±10 ppm across a wide input voltage range and that both the INL and the THD are also relatively flat over a wide temperature range.

AC- vs. DC-COUPLED SOLUTION

The CN-0540 is aimed at dc-coupled application scenarios, where the dc component of the signal must be preserved or where the response of the system must be maintained down to frequencies below 1 Hz and lower. For this reason, the system is designed to handle the large dc bias of the IEPE sensor.

However, some systems may not require the response down to dc, and in those scenarios, an ac-coupled input channel is acceptable.

The main difference between the two solutions is complexity of a signal chain and precision at dc and low frequencies. Whereas the ac-coupled solution requires less complexity, it lacks precision at low frequencies.

The user can adapt this design to an ac-coupled design by inserting a coupling capacitor in series with the input resistor. Refer to the schematic files in the design support package for more information.

Inserting a coupling capacitor has the effect of changing the input response to a high-pass response, where the pole frequency is typically chosen to be much less than 0 Hz. This filter not only blocks the dc bias current but also removes some of the 1/f noise. The dynamic range of the ac-coupled system appears higher than the dc-coupled version, but this is only due to the removal of the low frequency noise. The tradeoff for this comes at the cost of reduced sensitivity to low frequency vibration measurement data.

A higher noise is also expected in dc-coupled solutions due to the DAC output and lack of a high-pass filter at the input of the signal chain. Figure 14 shows the response of the CN-0540 when ac-coupled with a high-pass cutoff frequency at 1 Hz. The measurement was taken with the shorted input of the signal chain and enabled constant current source, with the ADC in a low power mode, MCLK/16, and FIR filter with a decimation of 32, as per the dc-coupled measurements.

If implementing an ac-coupled solution, the correct type of capacitor must be selected to achieve the best performance. Ceramic capacitors, in general, suffer from noise production due to the piezoelectric effect, and nonlinearity due to voltage coefficient (change of the relative permittivity with respect to applied voltage) and dielectric absorption. Tantalum capacitors offer reasonable performance, and a wide range of capacitance values are manufactured as high as hundreds of μF. The tantalum capacitor in an ac-coupled scenario can achieve THD performance at a similar level to a dc-coupled system, but only at frequencies higher than 10 Hz. For accurate representation of lower frequency vibration, the dc-coupled version is preferred.

SYSTEM POWER

The CN-0540 is provided with an optimal power solution that allows the complete signal chain to be powered from a single 3.3 V rail.

Power Solution

Figure 15 shows a simplified block schematic of the power section of the CN-0540. For compatibility with microcontroller and other development boards with Arduino style connections, the power solution for the board has been designed to run from a single 3.3 V supply, which is typically provided by Arduino-compatible boards.

To ensure stability of the system, the microcontroller board should be able to supply at least 250 mA to the vibration monitoring board through the 3.3 V supply. This is in addition to any supply current that the microcontroller board itself takes from this supply.

Although the CN-0540 evaluation board does not need 250 mA in steady state operation, during the initial power-up phase, there may be inrush currents up to 200 mA or higher for up to 30 ms. If the microcontroller board cannot sustain this current, it may lead to a reset occurring on the microcontroller board. Check the current output specification for the microcontroller board if unexpected resets occur.

The power solution comprises three voltage domains: the 3.3 V domain, the 5 V domain, and the 26 V domain. It also includes the 2.5 mA current source for the IEPE sensor.

Arduino-compatible boards provide the IOREF supply that the CN-0540 uses directly, therefore, no power solution is needed. IOREF provides the digital interface supply to the AD7768-1 (IOVDD) and powers the 16.384 MHz master clock source.

The CN-0540 is compatible with IOREF voltages down to 1.8 V, allowing the CN-0540 board to interface to microcontroller boards with lower logic levels.

The purpose of the provided power solution circuitry is to allow the CN-0540 board to run from a single low voltage supply, which is typically available on a microcontroller board, and to generate the other required voltage rails from that one supply. On the CN-0540, the raw 3.3 V input supply rail is used directly to provide the digital interface logic power to the AD7768-1 (AVDD2 supply), and also provides the power to the dc-to-dc stages, which boost the voltage to 5 V and 26 V.

The first dc-to-dc stage boosts the 3.3 V to 7 V and then regulates to 5 V by the combination of the LTC3459 and ADP7118 devices to provide the clean supply rails required by the AD7768-1, the LTC2606, and the ADR4540 reference, as well as the associated amplifier stages.

The second dc-to-dc stage boosts the 3.3 V to 28 V, and then regulates to 26 V by the combination of the LT3494 and LT3008 devices. This clean 26 V rail is required to supply the LT3092 current source that provides the IEPE sensor with 2.5 mA at up to 26 V.

Power Measurements

Power measurements were taken directly from the 3.3 V and IOREF supply rails. The power measurements, therefore, include the contributions from the power solution components themselves.

The current to the 26 V rail is constant due to the constant current source and does not vary with ADC settings.

The power consumption of the rest of the system was measured in the different operation modes of the ADC. A 1 kΩ load resistor was placed at the input of the signal chain, to allow a path for the current flow from the constant current source and to maintain a dc bias at the input of the AD8605.

Power Consumption

The most significant register settings on the ADC that affect the power consumption are

• Power mode
• MCLK divider
• MCLK frequency
• Filter type
• Decimation ratio of the filter
• VCM pin output divider
• Analog input precharge buffers
• Reference buffers
• General-purpose input/outputs (GPIOs)

System Default Configuration

A default configuration of the system for narrow bandwidth measurement was chosen as follows for the ADC settings:

• MCLK divider: MCLK/16
• Power mode: low power mode
• FIR filter with decimation over 32
• VCM pin output: (AVSS − AVDD)/2
• Reference (REF) buffers: precharge on
• Analog input (AIN) buffers: precharge on
• MCLK frequency of 16.384 MHz
• FDA enabled, in low power mode
• DAC buffer enabled
• DAC output set to half scale

The system default configuration was used for most of the measurements included in this reference design.

The analog input and reference input buffers on the AD7768-1 are set to precharge mode. The ADA4945-1 FDA is set to low power mode. In full power mode, the FDA can provide wider bandwidth and better linearity performance. However, because the bandwidth of interest in this design is less than 50 kHz, low power mode is sufficient. By enabling the AD7768-1 internal precharge buffers, better linearity and better noise performance are achieved without significantly increasing the system power. For more information about matching driver amplifiers and using the input buffering options on the AD7768 family, see the Application Note AN-1384.