Clock Generation and Distribution
Analog Devices offers ultralow jitter clock distribution and clock generation products for wireless infrastructure, instrumentation, broadband, ATE, and other applications demanding sub picosecond performance. ADI clock products are ideal for clocking high performance analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). ADI clock ICs integrate PLL cores, dividers, phase offset, skew adjust, and clock drivers in small chip scale packages.
Subcategories
Product Selection Table
Latest Resources
Application Notes
- AN-2072: AD9545 EEPROM Management (Rev. 0) PDF
- AN-501: Aperture Uncertainty and ADC System Performance (Rev. A) PDF
- AN-0983: Introduction to Zero-Delay Clock Timing Techniques PDF
- AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0) PDF
- AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0) PDF
Press Releases
Demo Board Schematic
Technical Articles
- Power-Up Phase Determinism Using Multichip Synchronization Features in Integrated Wideband DACs and ADCs
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Open-Source LIDAR Prototyping Platform
Analog Dialogue
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Phase-Locked Loop (PLL) Fundamentals
Analog Dialogue
- High Speed Converters: An Overview of What, Why, and How
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Dual-Loop Clock Generator Cleans Jitter, Provides Multiple High-Frequency Outputs
Analog Dialogue
Circuit Note
Design Tools
Solutions Bulletins & Brochures
Videos
- 16 Channel Tx/Rx S-Band Phased Array RADAR Platform
- Perfection of Translation Loop: Eliminating Spurious Signals
- 16Tx/16Rx L/S-Band Phased Array Radar & EW Prototyping Platform
- AD-FMCLIDAR1-EBZ: LIDAR Developmemt Platform by Analog Devices
- ADI: Hybrid-Beamforming Phased-Array Antenna-to-Bits Capability
Tutorials
Frequently Asked Questions
- What clock frequency comes out of the AD9510 outputs when you first apply power to the device?
- What is the fan-out capability of the CMOS, LVDS, and LVPECL outputs?
- Using the "ADC SNR method", what is the equivalent bandwidth for the jitter specification?
- What's the advantage of a DDS-based clock generator?
- What is the fine delay adjust which is available on certain LVDS/CMOS outputs?