Clock Generation & Distribution
Analog Devices offers ultralow jitter clock distribution and clock generation products for wireless infrastructure, instrumentation, broadband, ATE, and other applications demanding sub picosecond performance. ADI clock products are ideal for clocking high performance analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). ADI clock ICs integrate PLL cores, dividers, phase offset, skew adjust, and clock drivers in small chip scale packages.
Subcategories
Product Selection Table
Latest Resources
Application Notes
- Multicarrier TD-SCMA Feasibility (Rev. AN-0974) PDF
- AN-501: Aperture Uncertainty and ADC System Performance (Rev. A) PDF
- AN-0983: Introduction to Zero-Delay Clock Timing Techniques PDF
- AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0) PDF
- AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0) PDF
- AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0) PDF
- AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0) PDF
- AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0) PDF
- AN-0982: The Residual Phase Noise Measurement (Rev. 0) PDF
- AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0) PDF
- AN-1051: Reference Design for the AD9552 Oscillator Frequency Upconverter (Rev. 0) PDF
- AN-1066: Power Supply Considerations for AD9523, AD9524, and AD9523-1 Low Noise Clocks (Rev. A) PDF
- AN-1079: Determining the Maximum Tolerable Frequency Drift Rate of the AD9548 System Clock in Low Loop Bandwidth Applications (Rev. A) PDF
- AN-1061: Behavior of the AD9548 Phase and Frequency Lock Detectors in the Presence of Random Jitter (Rev. 0) PDF
- AN-1064: Understanding the Input Reference Monitors of the AD9548 (Rev. 0) PDF
- AN-741: Little Known Characteristics of Phase Noise (Rev. 0) PDF
Technical Articles
- High Speed Converters: An Overview of What, Why, and How
- JESD204B Subclasses (Part 1): An Introduction to JESD204B Subclasses and Deterministic Latency
- JESD204B Subclasses (Part 2): Subclass 1 vs. Subclass 2 System Considerations
- Dual-Loop Clock Generator Cleans Jitter, Provides Multiple High-Frequency Outputs
- Clocking Requirements for High Speed Data Converters
- Low-power direct digital synthesizer cores enable high level of integration
- Improved DDS Devices Enable Advanced Comm Systems
- ADI Buys Korean Mobile TV Chip Maker
- Design A Clock-Distribution Strategy With Confidence
- Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems
- Speedy A/Ds Demand Stable Clocks
User Guides
- UG-406: Evaluation Board for the ADF4150HV PLL Frequency Synthesizer PDF
- UG-551: XStream™ ADI-BERT: An 11.3 Gbps Bit Error Rate Tester Solution Based on ADN2915, a Continuous-Tuning Wideband Clock and Data Recovery IC PDF
- UG-311: Reliability Handbook PDF
- UG-485: Evaluation Board for the ADF4153A Fractional-N PLL Frequency Synthesizer PDF
- UG-380: Evaluation Board for the ADF4150 PLL Frequency Synthesizer PDF
- UG-369: Evaluation Board for the ADF4151 PLL Frequency Synthesizer PDF
- UG-203: Evaluating the AD9550 Integer-N Clock Translator PDF
- UG-169: Evaluating the AD9523/AD9524 Clock Generator PDF
- UG-125: Setting Up the Evaluation Board for the ADCLK944 PDF
- UG-035: Evaluating the AD9552 Oscillator Frequency Upconverter PDF
- UG-075: AD9516-x, AD9517-x, and AD9518-x Evaluation Board User Guide PDF
- UG-071 Evaluation Board User Guide PDF
- UG-070 Evaluation Board User Guide PDF
- UG-069: Setting Up the Evaluation Board for the ADCLK946 PDF
- UG-066: Setting Up the Evaluation Board for the ADCLK954 PDF
- UG-068: Setting Up the Evaluation Board for the ADCLK948 PDF
- UG-058: Setting Up the Evaluation Board for the ADCLK914 PDF
- UG-006: Setting Up the Evaluation Board for the ADCLK905/ADCLK907/ADCLK925 PDF
Evaluation Documentation
- AD9516-5 Bill of Materials (Rev. D) XLS
- AD9516-4 Bill of Materials (Rev. D) XLS
- AD9516-3 Bill of Materials (Rev. D) XLS
- AD9516-2 Bill of Materials (Rev. D) XLS
- AD9516-1 Bill of Materials (Rev. D) XLS
- AD9516-0 Bill of Materials (Rev. D) XLS
- AD9511/AD9512 All Layers (Rev. B) PDF
- AD9511/AD9512 Schematics (Rev. B) PDF
- AD9511/AD9512 Gerber Files (Rev. B) ZIP
- AD9512 Evaluation Board Bill of Materials, Rev. B (Pb-Free) XLS
Circuit Notes
Design Tools
Solutions Bulletins & Brochures
Videos
Tutorials
Press Releases
Informational
Frequently Asked Questions
- What clock frequency comes out of the AD9510 outputs when you first apply power to the device?
- What is the fan-out capability of the CMOS, LVDS, and LVPECL outputs?
- Using the "ADC SNR method", what is the equivalent bandwidth for the jitter specification?
- What's the advantage of a DDS-based clock generator?
- What is the fine delay adjust which is available on certain LVDS/CMOS outputs?
- Are the ADI clock parts stand-alone clock sources or do I still have to buy a clock source to drive these parts?
- Does the fine delay adjust affect the jitter?
- How do harmonic spurs in the output spectrum affect jitter (random or deterministic)?
- How do I optimize my PLL loop for the best phase noise and/or jitter?
- My circuit board has both an analog GND and a digital GND. How should I connect the AD9510 pins labeled GND?
- My applications are RF, not for clocking data converters. Can ADI's 951X ICs be used for RF applications?
- I am not using the CLK1 input on the AD9510. Can I just leave it floating?
- If I change the level of PECL output, does it affect the jitter?
- I have an input present at the clock input, but I'm not seeing an output?
- Can I tri-state the AD9510 outputs?
- Why doesn't the mini-divider support the divide ratio I want?
- Why doesn't the PLL make my reference input and the clock outputs line up?
- Why do you recommend AC coupling, rather than DC coupling, at the clock inputs?
- What are the best clock sources for a distribution-only design?
- What happens to the AD9510/11 clock outputs if the Reference Input (REFIN) signal goes away?
- What is the best way to terminate LVPECL outputs to get lowest jitter?
- What are some of the advantages/disadvantages of using LVPECL vs. LVDS outputs?
- What is the proper termination (value and location) for outputs?
- Can I run CMOS outputs at 5V?
- Do divide ratios change the propagation delay?
- Do you guarantee performance shown in ADIsimCLK?
- Help! My PLL came unlocked over temperature.
- Can I use the 951X clocks to drive a mixer (RF LO)?
- Do different divide ratios cause variations in jitter?
- How do I feed a single-ended signal into a differential input?
- How can I determine the die temperature of your device?
- On the AD9510, how can I make sure that the duty cycle of output clocks stays within 40% to 60% duty cycle window?
- Is there a way to cause Input/Output rising edges to be synchronous (zero delay) with the AD9510/11?
- Is there any reason to use a transformer on a differential clock output to obtain a "clean" single-ended clock output?
- Is there any difference between the nature of an oscillator's phase noise and the phase noise from a clock chip?
- On the AD9510, what is the relationship between clock output jitter and CLK1/CLK2 input slew rate?
- Is it possible to impedance match a clock output if it is heavily loaded? (e.g. CL=100pF)
- On my board, I can't get the same low jitter numbers that are shown in the datasheet. Am I doing something wrong?
- How good does my input signal need to be?
- I have a clocking scheme which requires several different division ratios simultaneously. I have a frequency plan, but I'm concerned about crosstalk. How much of a problem is this with your clock distribution chips?
- Is it ok for me to connect the same power supply to both the charge pump and distribution power supply pins?
- I'm trying to write to the part in single-byte mode, but I can't write anything. What am I doing wrong?
- I turned off my reference but the Digital Lock Detect (DLD) still says I'm locked.
- How do I use a VCO with a supply greater than 5V?
- How long does it take for the PLL to lock?
- I want to use the phase offset feature on the AD9510 dividers to generate two signals 90° out of phase. How accurate is the phase offset?
- I really need >10 clock outputs. Can I use multiple chips together and still guarantee that all output clocks are synchronized to REFIN?
- Why is my phase noise shape changing when I change the PLL settings?
- Can I shift the threshold on clocks for single-ended inputs?
- Which provides better performance - a clock source with sinewave output, or one with differential square wave outputs?
- Why do I see reference spurs?
- Why is the fine delay adjust not available on all the outputs?
- Will the AD9510 work without a reference input signal?
- Why can I not get the same output amplitude or rise and fall times as stated in your datasheet?
- Why should I use differential rather than single-ended?
- Will differential or single-ended inputs/outputs improve my jitter?
- What suppliers do you recommend for VCO/VCXOs?
- Why does the AD9540 require special filtering on its analog output. What are the requirements of this filter?
- What happens if I run the part in an ambient environment which exceeds 85°C?
- What is the effect of distributing harmonically related clocks (on chip or on board) in terms of jitter?
- What is the difference between the coarse phase adjust and the fine delay adjust?
- How do you specify jitter?
- Do VCXOs have better phase noise and jitter performance than VCOs?
- How do the PLLs in the AD951x parts compare to other ADI PLLs?
- How do I use the clock part for jitter clean-up?
- Who do I contact for technical support on ADIsimCLK?
- What PCB layout recommendations do you have for the of the exposed paddle on the bottom side of the LFCSP package?
- When a jitter number is specified without an associated bandwidth, what bandwidth should be assumed?
- Why can't I use a bandpass filter for my loop filter?
- Why don't you spec psrr and cmrr in the datasheet?
- Can I use different power supply voltages for the PECL output drivers?
- Why do I want to run a fast PFD frequency?
- Are outputs short-circuit protected?
- What should I do with unused channels on the AD9510?
- How do I get two AD951x (with PLL) to synchronize to the same reference input edge?
- How do I determine if a VCO is good enough for my purpose?
- How do you determine the bandwidth over which phase noise is integrated to obtain jitter?
- Does jitter vary with different clock frequencies? How about phase noise?
- Does the AD9510 support 2.5V PECL?
- How does the clock clean-up function of the AD951x parts work?
- How do I know which VCO will work best with the AD9510?
- How do I synchronize multiple clock devices?
- The AD9510 datasheet says to use an external pull-up resistor on the FUNCTION pin. Why do I need this and what range of resistors will work?
- Should I reference the passive filter to ground? or supply?
- On the AD951x clock ICs, does the phase offset (coarse delay) affect the jitter?
- May I use the AD9540 for spread spectrum clocking?
- The reference input is differential, but my reference is single-ended. Do I need to convert to differential to drive the AD9510?
- Should I tie my loop filter to ground or PLL supply?
- Is there an advantage to running a higher VCO frequency than the output frequency?
- Should I use the minimum charge pump current settings in order to minimize power?
- The loop filter was working great until I changed the divide ratio in PLL. What happened?
- My application has pretty tight power consumption requirements. I am very interested in the capabilities of the AD9510, but I don't need every feature. Is it possible to turn off the unused features and save power?
- My loop is not locking. How do I debug this?
- Some of the schematics in the AD951x data sheets show an LVPECL termination scheme which is different from the classic termination often seen (50 Ω to Vs - 2V, or the Thevenin equivalent thereof). How does this work, and how did you chose 200 Ω for the resistors? Can I use 100 ohms to improve the slew rate (or jitter)?
- How do I choose between active and passive filter in PLL loop?
- I sure can't measure jitter with femtosecond resolution on my scope! How do you do it? How much confidence do you have in the jitter figures that you are quoting for these parts?
- Is .01 uF sufficient for power supply pin bypass?
- If I use only one of the PECL differential outputs and the unused output is terminated in 50Ω, how will this affect the phase noise or jitter of the single-ended output?
- Is it okay to AC-couple PECL or LVDS outputs?
- How much bandwidth is required to process a PECL or LVDS output?
- I changed the coarse phase adjust in the evaluation software, but nothing happened. What's going on?
- I want to use the variable delay adjust, but the jitter is too high. What can I do?
- I have pulled SYNCB low, but I still have output from a channel. Why?
- I'm working with optical networks - SONET/SDH. Do ADI's clock chips support these applications?
- If jitter can be calculated from phase noise measurements, is it possible to calculate phase noise from jitter numbers?
- Can I get two clock outputs from the AD9540?
- Are the CMOS drivers on the clock devices complementary?
- I ran the AD9510 outputs at 1.4 GHz and they seem to work fine. Is there a problem running them at 1.4 GHz?
Clock Generation & Distribution
| SortOrder | Part# | # Outputs | Clock Function | Interface | On-Chip VCO or DCO | Output Frequency (max) (Hz) | Output Logic | Power (typ) (W) | Ref Clock (min) (Hz) | Ref Clock (max) (Hz) | Price (1000+) ($ US) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | LTC6955-1 | 11 | Distribution | SPI | No | 7.5G | CML | 1.3 | - | - | $8.61 (LTC6955IUKG-1#PBF) |
| 2 | LTC6955 | 11 | Distribution | SPI | No | 7.5G | CML | 1.3 | - | - | $8.61 (LTC6955IUKG#PBF) |
| 3 | LTC6952 | 11 | Generation, Synchronization | SPI | - | 4.5G | CML | 2.6 | 1M | 500M | $15.88 (LTC6952IUKG#PBF) |
| 4 | LTC6953 | 11 | Distribution | SPI | No | 4.5G | CML | 2 | - | - | $13.90 (LTC6953IUKG#PBF) |
| 5 | AD9544 | 10 | Generation, Synchronization | I²C, Serial, SPI | Yes | 500M | CML, HCSL, LVDS | 560m | 1 | 750M | $10.48 (AD9544BCPZ) |
| 6 | AD9543 | 10 | Generation, Synchronization | I²C, Serial, SPI | Yes | 500M | CML, HCSL, LVDS | 560m | 2k | 750M | $8.98 (AD9543BCPZ) |
| 7 | AD9542 | 10 | Generation, Synchronization | I²C, Serial, SPI | Yes | 500M | CML, HCSL, LVDS | 560m | 2k | 750M | $7.48 (AD9542BCPZ) |
| 8 | AD9545 | 10 | Generation, Synchronization | I²C, Serial, SPI | Yes | 500M | CML, HCSL, LVDS | 560m | 1 | 750M | $14.96 (AD9545BCPZ) |
| 9 | AD9576 | 11 | Distribution, Generation | I²C, Pin Select, Serial, SPI | Yes | 1.25G | CMOS, HCSL, HSTL, LVDS | 619m | 8k | 325M | $3.45 (AD9576BCPZ) |
| 10 | LTC6951-1 | 5 | Distribution, Generation | SPI | Yes | 2.7G | CML, LVDS | 1.1 | 1M | 425M | $8.75 (LTC6951IUHF-1#PBF) |
| 11 | LTC6951 | 5 | Distribution, Generation | SPI | Yes | 2.5G | CML, LVDS | 1.1 | 1M | 425M | $8.75 (LTC6951IUHF#PBF) |
| 12 | HMC6832 | 8 | Distribution | Pin Select | No | - | LVDS, LVPECL | 1 | 10M | 3.5G | - |
| 13 | AD9530 | 4 | Generation | Serial | Yes | 2.7G | CML | 2.3 | 6M | 800M | $25.41 (AD9530BCPZ) |
| 14 | HMC7043 | 14 | Distribution | SPI | No | 3.2G | CML, LVCMOS, LVDS, LVPECL | 1.5 | 200M | 6G | - |
| 15 | HMC7044 | 14 | Generation | SPI | Yes | 3.2G | CML, LVCMOS, LVDS, LVPECL | 3.4 | 0.00015M | 3.2G | - |
| 16 | AD9531 | 24 | Generation | Pin Select, SPI | Yes | 400M | CMOS, HSTL, LVDS | 600m | 9.5M | 260M | $11.90 (AD9531BCPZ) |
| 17 | LTC6954-4 | 3 | Distribution | SPI | No | 1.4G | LVPECL | 930m | 0 | 1.4G | $7.50 (LTC6954IUFF-4#PBF) |
| 18 | LTC6954-3 | 3 | Distribution | SPI | No | 1.4G | LVPECL | 930m | 0 | 1.4G | $7.50 (LTC6954IUFF-3#PBF) |
| 19 | LTC6954-2 | 3 | Distribution | SPI | No | 1.4G | LVPECL | 930m | 0 | 1.4G | $7.50 (LTC6954IUFF-2#PBF) |
| 20 | LTC6954-1 | 3 | Distribution | SPI | No | 1.4G | LVPECL | 990m | 0 | 1.4G | $8.25 (LTC6954IUFF-1#PBF) |
| 21 | AD9578 | 4 | Generation | Serial, SPI | Yes | 919M | HCSL, LVCMOS, LVDS, LVPECL | 618m | 20M | 60M | $7.54 (AD9578BCPZ) |
| 22 | AD9574 | 7 | Generation | Pin Select | Yes | 312.5M | CMOS, HCSL, HSTL, LVDS | 569m | 19.44M | 25M | $3.06 (AD9574BCPZ) |
| 23 | AD9528 | 14 | Generation | I²C, Serial, SPI | Yes | 1.25G | HSTL, LVDS | 1.675 | - | 400M | $8.25 (AD9528BCPZ) |
| 24 | AD9554-1 | 4 | Synchronization | I²C, Serial, SPI | Yes | 941M | HCSL, LVDS, LVPECL | 920m | 2k | 1G | $20.81 (AD9554-1BCPZ) |
| 25 | AD9554 | 8 | Synchronization | I²C, Serial, SPI | Yes | 941M | HCSL, LVDS, LVPECL | 940m | 2k | 1G | $21.33 (AD9554BCPZ) |
| 26 | LTC6950 | 5 | Distribution, Generation | SPI | PLL on Chip | 1.4G | CMOS, LVDS, LVPECL | 1.3 | 0 | 250M | $9.95 (LTC6950IUHH#PBF) |
| 27 | LTC6957-4 | 2 | Clock Buffer | - | No | 300M | Complementary CMOS | 59.4m | - | 300M | $3.60 (LTC6957IMS-4#PBF) |
| 28 | LTC6957-3 | 2 | Clock Buffer | - | No | 300M | In Phase CMOS | 59.4m | - | 300M | $3.60 (LTC6957IDD-3#PBF) |
| 29 | LTC6957-2 | 2 | Clock Buffer | - | No | 300M | LVDS | 59.4m | - | 300M | $3.60 (LTC6957IMS-3#PBF) |
| 30 | LTC6957-1 | 2 | Clock Buffer | - | No | 300M | LVPECL | 59.4m | - | 300M | $3.60 (LTC6957IMS-1#PBF) |
| 31 | AD9508 | 4 | Distribution | I²C, Pin Select, Serial | No | 1.65G | CMOS, HSTL, LVDS | 500m | 0M | 1.65G | $3.98 (AD9508BCPZ) |
| 32 | AD9525 | 8 | Generation | Serial, SPI | No | 3.6G | CMOS, LVPECL | 1.2 | 0M | 500M | $8.33 (AD9525BCPZ) |
| 33 | HMC1035 | 1 | Distribution, Generation | SPI | Yes | 2500M | LVDS, LVPECL | 0.57 | - | 350 | - |
| 34 | AD9559 | 4 | Synchronization | I²C, Serial, SPI | Yes | 1.25G | HSTL, LVDS | 710m | 2k | 1.25G | $19.26 (AD9559BCPZ) |
| 35 | HMC988 | 1 | Delay, Divider | SPI | No | 4G | LVPECL | 0.2244 | 0 | 4G | - |
| 36 | HMC1033 | 1 | Distribution, Generation | SPI | Yes | 550M | LVDS, LVPECL | 0.64 | - | 350 | - |
| 37 | HMC911 | 1 | Delay | Pin Select | No | 24G | - | 1600m | - | 24G | - |
| 38 | HMC1034 | 1 | Distribution, Generation | SPI | Yes | 3000M | CML | 0.86 | - | 350 | - |
| 39 | HMC1032 | 1 | Distribution, Generation | SPI | Yes | 350M | CML | 0.86 | - | 350 | - |
| 40 | HMC1031 | 1 | Distribution, Generation | SPI | No | 500M | - | 0.005 | - | 140 | - |
| 41 | AD9577 | 4 | Generation | I²C | Yes | 637.5M | CMOS, LVDS, LVPECL | 1 | 19.44M | 54M | $4.34 (AD9577BCPZ) |
| 42 | AD9558 | 6 | Synchronization | I²C, Pin Select, Serial, SPI | Yes | 1.25G | CMOS, HSTL, LVDS | 740m | 2k | 1.25G | $16.25 (AD9558BCPZ) |
| 43 | AD9557 | 2 | Synchronization | I²C, Pin Select, Serial, SPI | Yes | 1.25G | CMOS, HSTL, LVDS | 550m | 2k | 1.25G | $15.00 (AD9557BCPZ) |
| 44 | HMC987 | 9 | Distribution | Parallel, SPI | No | 8G | LVPECL | 0.7722 | - | - | - |
| 45 | HMC959 | 1 | Divider | Pin Select | No | 26G | CML | 281m | - | - | - |
| 46 | HMC877 | 1 | Delay | Pin Select | No | 23G | - | 627m | 8G | 23G | - |
| 47 | HMC859 | 1 | Divider | Pin Select | No | 26G | CML | 320m | - | - | - |
| 48 | AD9550 | 2 | Generation | Pin Select | Yes | 810M | CMOS, LVDS, LVPECL | 450m | 8k | 200M | $3.40 (AD9550BCPZ) |
| 49 | AD9523-1 | 14 | Generation | I²C, Serial, SPI | Yes | 1G | HSTL, LVCMOS, LVDS, LVPECL | 898m | - | 400M | $8.67 (AD9523-1BCPZ) |
| 50 | AD9524 | 6 | Generation | I²C, Serial, SPI | Yes | 1G | HSTL, LVCMOS, LVDS, LVPECL | 559m | 42M | 400M | $6.00 (AD9524BCPZ) |
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