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Features and Benefits
- Output frequency range: 800 MHz to 12.8 GHz
- Jitter < 30 fsRMS
- Wideband Noise Floor: -160 dBc/Hz @12.8 GHz
- PLL Specifications:
- Normalized In-Band Phase Noise Floor:
- -239 dBc/Hz: Integer
- -237 dBc/Hz: Fractional Mode
- In-Band 1/f Noise
- -287 dBc/Hz: Normalized to 1Hz
- -147 dBc/Hz: Normalized to 1GHz at 10 kHz
- 625 MHz Phase Detector Frequency Integer Mode
- 250 MHz Phase Detector Frequency Fractional Mode
- 25-bit fixed, 49-bit combined Fractional modulus
- 4 GHz Reference Input Frequency
- Typical -95 dBc PFD spurs
- Reference to Output Delay Specifications:
- Part-to-Part Standard Deviation: 10ps
- Temperature Drift: 0.06ps/°C
- Adjustment Step Size: <1ps
- Multi-chip Output Phase Alignment via SYNC pin or by EZSync method
- 3.3V and 5V Power supplies
- ADIsimPLLTM Loop Filter Design Tool Support
- 7mm x 7mm 48 Lead LGA
- -40°C to 125°C Operating Junction Temperature
The ADF4368 is a high performance, ultralow jitter, integer-N and fractional-N phase-locked loop (PLL) with integrated VCO ideally suited for frequency conversion applications.
The high performance PLL has a figure of merit of -239dBc/Hz, very low 1/f Noise of normalized -287dBc/Hz and high PFD frequency that can achieve ultralow in-band noise and integrated jitter. The ADF4368 can generate any frequency from 800 MHz to 12.8 GHz without an internal doubler, thereby eliminating the need for sub-harmonic filters. Σ-Δ modulator includes a 25-bit fixed modulus which allows hertz frequency resolution and an additional 24-bit variable modulus which allows even finer resolution and flexibility for frequency planning. 9 dBm output power at 12.8 GHz in single ended configuration with 16 step power adjust feature makes it very useful for any application.
For multiple frequency conversion applications such as phase array radar or massive MIMO systems, the outputs of multiple ADF4368 can be aligned by using SYNC input or EZSync. EZSync method is used when it is difficult to distribute the SYNC signal to all parts precisely. For applications that require deterministic delay or delay adjustment capability, a programmable reference to output delay with <1ps resolution is provided. The reference to output delay is guaranteed across multiple devices and temperature, allowing for predictable and precise multichip alignment.
The simplicity of the ADF4368 block diagram eases development time with a simplified SPI register map, external SYNC input and repeatable multi-chip phase alignment both in integer and fractional mode.
For more information please contact ADI at ADF_NewProducts@analog.com
Product Lifecycle Pre-Release
This product is new and engineering validation may still be underway. Quantities may be limited and design specifications may change while we ready the product for release to production.
Tools & Simulations
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