ADF4193
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ADF4193

Low Phase Noise, Fast Settling PLL Frequency Synthesizer

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Info: : PRODUCTION tooltip
Info: : PRODUCTION tooltip
Part Details
Part Models 4
1ku List Price Starting From $6.00
Features
  • New, fast settling, fractional-N PLL architecture
  • Single PLL replaces ping-pong synthesizers
  • Frequency hop across GSM band in 5 µs with phase settled by 20 µs
  • 0.5° rms phase error at 2 GHz RF output
  • Digitally programmable output phase
  • RF input range up to 3.5 GHz
  • 3-wire serial interface
  • On-chip, low noise differential amplifier
  • Phase noise figure of merit: –216 dBc/Hz
  • Loop filter design possible using ADIsimPLL™
  • Qualified for automotive applications
Additional Details
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The ADF4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations. It consists of a low noise, digital phase frequency detector (PFD), and a precision differential charge pump. There is also a differential amplifier to convert the differential charge pump output to a single-ended voltage for the external voltage-controlled oscillator (VCO).

The Σ-Δ-based fractional interpolator, working with the N divider, allows programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler allow selectable reference signal (REFIN) frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles inside the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases cost, complexity, PCB area, shielding, and characterization on previous ping-pong GSM PLL architectures.

Applications

  • GSM/EDGE base stations
  • PHS base stations
  • Instrumentation and test equipment
Part Models 4
1ku List Price Starting From $6.00

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Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
ADF4193BCPZ
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ADF4193BCPZ-RL
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ADF4193BCPZ-RL7
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ADF4193WCCPZ-RL7
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Product Lifecycle

PCN

Jul 5, 2022

- 21_0271

Qualification of an Alternate Adhesive Material and Molding Compound for Select LFCSP Packages

Oct 18, 2016

- 16_0036

Assembly Relocation to Stats ChipPAC Jiangyin and Test Transfer to Stats ChipPAC Singapore of Select LFCSP Products

Aug 6, 2014

- 13_0230

Assembly and Test Transfer of Select 3.5x3.5, 4x3, 4x4, and 5x5mm LFCSP Products to STATS ChipPAC China

Mar 7, 2012

- 10_0241

Conversion of LFCSP package outline from Punch to Sawn of package sizes 4x4, 5x5, 6x6 and 7x7mm and a transfer of assembly site.

May 4, 2016

- 14_0178

Conversion of 3x3mm, 4x4mm and 5x5mm LFCSP Package Outlines from Punch to Sawn and Transfer of Assembly Site to Amkor Philippines

Filter by Model

reset

Reset Filters

Part Models

Product Lifecycle

PCN

Jul 5, 2022

- 21_0271

arrow down

Qualification of an Alternate Adhesive Material and Molding Compound for Select LFCSP Packages

Oct 18, 2016

- 16_0036

arrow down

Assembly Relocation to Stats ChipPAC Jiangyin and Test Transfer to Stats ChipPAC Singapore of Select LFCSP Products

Aug 6, 2014

- 13_0230

arrow down

Assembly and Test Transfer of Select 3.5x3.5, 4x3, 4x4, and 5x5mm LFCSP Products to STATS ChipPAC China

Mar 7, 2012

- 10_0241

arrow down

Conversion of LFCSP package outline from Punch to Sawn of package sizes 4x4, 5x5, 6x6 and 7x7mm and a transfer of assembly site.

May 4, 2016

- 14_0178

arrow down

Conversion of 3x3mm, 4x4mm and 5x5mm LFCSP Package Outlines from Punch to Sawn and Transfer of Assembly Site to Amkor Philippines

Software & Part Ecosystem

Software & Part Ecosystem

Evaluation Kit

Evaluation Kits 1

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EVAL-ADF4193

ADF4193 Evaluation Boards

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EVAL-ADF4193

ADF4193 Evaluation Boards

ADF4193 Evaluation Boards

Product Detail

This page contains ordering information for the evaluation board used to evaluate the ADF4193 Low Phase Noise, Fast Settling PLL Frequency Synthesizer.


This evaluation board requires an SDP Controller board for connection to the PC. The SDP controller board connects to the PC via USB 2.0. The evaluation board will connect to the SDP controller board. The evaluation board cannot be connected directly to the PC. The evaluation software running on the PC will communicate through the SDP Controller board, to the evaluation board. The SDP Controller board is a separate list item in the ordering guide below (EVAL-SDP-CS1Z). If you have not previously purchased an SDP Controller board, please do so to ensure a full evaluation setup.

Tools & Simulations

Tools & Simulations 2

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