AD9559

RECOMMENDED FOR NEW DESIGNS

Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator

Data Sheet (Rev. D) Product Selection Table

Part Models: 2
1ku List Price: Starting From $27.25

Viewing:

Overview

Supports GR-1244 Stratum 3 stability in holdover mode
Supports smooth reference switchover with virtually no disturbance on output phase
Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems
Supports ITU-T G.8262 synchronous Ethernet node clocks
Supports ITU-T G.823, G.824, G.825, and G.8261
Auto/manual holdover and reference switchover
Adaptive clocking allows dynamic adjustment of feedback dividers for use in OTN mapping/demapping applications
Dual digital PLL architecture with four reference inputs (single-ended or differential)
4x2 crosspoint allows any reference input to drive either PLL
Input reference frequencies from 2 kHz to 1250 MHz

Reference validation and frequency monitoring (2 ppm)
Programmable input reference switchover priority
20-bit programmable input reference divider
4 pairs of clock output pins with each pair configurable as a single differential LVDS/HSTL output or as 2 single-ended CMOS outputs
Output frequencies: 262 kHz to 1250 MHz
Programmable 17-bit integer and 23-bit fractional feedback divider in digital PLL
Programmable digital loop filter covering loop bandwidths from 0.1 Hz to 2 kHz
Low noise system clock multiplier
Optional crystal resonator for system clock input
On-chip EEPROM to store multiple power-up profiles
Pin program function for easy frequency translation configuration
Software controlled power-down
72-lead (10 mm × 10 mm) LFCSP package

The AD9559 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9559 generates an output clock synchronized to up to four external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9559 continuously generates a low jitter output clock even when all reference inputs have failed.

The AD9559 operates over an industrial temperature range of −40°C to +85°C. If a single DPLL version of this part is needed, refer to the AD9557.

Applications

Network synchronization, including Synchronous Ethernet and OTN mapping/de-mapping
Cleanup of reference clock jitter
SONET/SDH clocks up to OC-192, including FEC
Stratum 3 holdover, jitter cleanup, and phase transient control
Wireless base station controllers
Cable infrastructure
Data communications

Part Models: 2
1ku List Price: Starting From $27.25

Documentation

Data Sheet 1

AD9559: Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator Data Sheet (Rev.D) 01/28/2025

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.

Part Model	Pin/Package Drawing	Documentation	CAD Symbols, Footprints, and 3D Models
AD9559BCPZ	72-Lead Lead Frame Chip Scale Package	Material Declaration Reliability Report Package Resources	Ultra Librarian SamacSys
AD9559BCPZ-REEL7	72-Lead Lead Frame Chip Scale Package	Material Declaration Reliability Report Package Resources	Ultra Librarian SamacSys

Part Models	Product Lifecycle	PCN

Jun 26, 2023 - 23_0025 Package Outline Drawing and Data Sheet Revision for Select LFCSP Products in Amkor
		PCN23_0025_Form Material_Report Package Outline Drawing Qualification Results Summary
AD9559BCPZ	PRODUCTION
AD9559BCPZ-REEL7	PRODUCTION
May 16, 2016 - 16_0028 CANCELLED: AD9559 Die revision
		PCN16_0028_Form Material_Report Qualification Results Summary
AD9559BCPZ	PRODUCTION
AD9559BCPZ-REEL7	PRODUCTION
Mar 12, 2015 - 14_0218 CANCELLED: AD9559 Die Revision
		PCN14_0218_Form Material_Report Qualification Plan
AD9559BCPZ	PRODUCTION
AD9559BCPZ-REEL7	PRODUCTION

This is the most up-to-date revision of the Data Sheet.

Software Resources

Can't find the software or driver you need?

Request a Driver/Software

Hardware Ecosystem

Parts	Product Life Cycle	Description
Clock ICs 4
AD9512	RECOMMENDED FOR NEW DESIGNS	1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs
AD9513	RECOMMENDED FOR NEW DESIGNS	800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs
AD9514	RECOMMENDED FOR NEW DESIGNS	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs
AD9515	RECOMMENDED FOR NEW DESIGNS	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

Fanout Buffers 5
ADCLK925	RECOMMENDED FOR NEW DESIGNS	Ultrafast SiGe ECL Clock/Data Buffers
ADCLK944	RECOMMENDED FOR NEW DESIGNS	2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer
ADCLK948	RECOMMENDED FOR NEW DESIGNS	Two Selectable Inputs, 8 LVPECL Outputs SiGe Clock Fanout Buffer
ADCLK854	RECOMMENDED FOR NEW DESIGNS	1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer
ADCLK846	RECOMMENDED FOR NEW DESIGNS	1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer
LDO Linear Regulators 1
ADP150	PRODUCTION	Ultralow Noise, 150 mA CMOS Linear Regulator
Switching Regulators & Controllers 1
ADP1829	PRODUCTION	Dual, Interleaved, Step-Down DC-to-DC Controller with Tracking

Tools & Simulations

IBIS Model 1

AD9559 IBIS Model

Evaluation Kits

AD9559 Evaluation Board

Buy Now View Details

Product Details

The AD9559 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9559 generates two completely independent output clocks that are synchronized to up to four external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9559 continuously generates a low jitter output clock even when all reference inputs have failed.

For convenience, detailed information from the AD9559 data sheet has been included here. Use this user guide in conjunction with the AD9559 data sheet and software documenta¬tion available at www.analog.com.

Features

Simple power connection using 6 V wall adapter and on-board LDO voltage regulators
LDOs are easily bypassed for power measurements
4 ac-coupled differential output SMA connectors (which can be reconfigured for up to 8 single-ended outputs.
4 inputs SMA connectors that accept either single-ended or differential signals
USB connection to PC
Microsoft Windows-based evaluation software with simple graphical user interface and support for both 64-bit and 32-bit operating systems.
Easy access to digital I/O and diagnostic signals via I/O header
Status LEDs for diagnostic signals