ADCLK854

RECOMMENDED FOR NEW DESIGNS

1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer

Part Models
2
1ku List Price
Starting From $6.10
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Part Details

  • 2 selectable differential inputs
  • Selectable LVDS/CMOS outputs
  • Up to 12 LVDS (1.2 GHz) or 24 CMOS (250 MHz) outputs
  • <12 mW per channel (100 MHz operation)
  • 54 fs rms integrated jitter (12 kHz to 20 MHz)
  • 100 fs rms additive broadband jitter
  • 2.0 ns propagation delay (LVDS)
  • 135 ps output rise/fall (LVDS)
  • 70 ps output-to-output skew (LVDS)
  • Sleep mode
  • Pin programmable control
  • 1.8 V power supply
ADCLK854
1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer
ADCLK854-FBL ADCLK854 Pin Configuration
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Documentation

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Tools & Simulations

ADCLK854 IBIS Models 2

  • ADCLK854 LVDS IBIS Model&#44; Ver 3.2
  • ADCLK854 CMOS IBIS Model&#44; Ver 3.2
  • ADIsimCLK Design and Evaluation Software

    ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.

    Open Tool

Evaluation Kits

EVAL-ADCLK854

ADCLK854 Evaluation Board

Product Details

The ADCLK854 data sheet contains full technical details about the specifications and operation of this device and should be consulted when using the evaluation board.

The ADCLK854 is a high performance clock fanout buffer. The evaluation board is fabricated using a high quality Rogers® dielectric material. Transmission line paths are kept as close to 100 Ω differentially as possible.

EVAL-ADCLK854
ADCLK854 Evaluation Board

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