AD9235: 12-Bit, 20/40/65 MSPS 3 V A/D Converter Data Sheet (Rev. D)11/15/20041328 kB
Features and Benefits
- Single +3 V Supply Operation (2.7 V to 3.6 V)
- SNR = 70 dBc to Nyquist at 65 MSPS
- SFDR = 85 dBc to Nyquist at 65 MSPS
- Low Power: 300 mW at 65 MSPS
- On-Chip Reference and SHA
- Differential Input with 500 MHz Bandwidth
- DNL of ±0.4 LSB
- Flexible Analog Input: 1 Vp-p to 2 Vp-p
- Offset Binary or Twos Complement Data Format
- Clock Duty Cycle Stabilizer
- Pin out Migration to Either AD9215, AD9236, AD9245
The AD9235 is a family of monolithic, single 3 V supply, 12-bit, 20/40/65 MSPS analog-to-digital converters. This family features a high performance sample-and-hold amplifier (SHA) and voltage reference. The AD9235 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 20/40/65 MSPS data rates and guarantee no missing codes over the full operating temperature range.
The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and offsets including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available analog-to-digital converters, the AD9235 is suitable for applications in communications, imaging, and medical ultrasound.
A single-ended clock input is used to control all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in straight binary or twos complement formats. An out-of-range (OTR) signal indicates an overflow condition that can be used with the most significant bit to determine low or high overflow.
Fabricated on an advanced CMOS process, the AD9235 is available in a 28-lead thin shrink small outline package (TSSOP) and a 32-lead chip scale package (LFCSP) and is specified over the industrial temperature range (-40°C to +85°C).
- Ultrasound equipment
- IF sampling in communications receivers
- Battery-powered instruments
- Hand-held scopemeters
- Low cost digital oscilloscopes
- The AD9235 operates from a single 3 V power supply and features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families.
- Operating at 65 MSPS, the AD9235 consumes a low 300 mW.
- The patented SHA input maintains excellent performance for input frequencies up to 100 MHz and can be configured for single-ended or differential operation.
- The AD9235 pinout is similar to the AD9214-65, a 10-bit, 65 MSPS ADC. This allows a simplified upgrade path from 10 bits to 12 bits for 65 MSPS systems.
- The clock DCS maintains overall ADC performance over a wide range of clock pulse widths.
- The OTR output bit indicates when the signal is beyond the selected input range.
Product Lifecycle Production
At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
Evaluation Kits (1)
This page contains evaluation board documentation and ordering information for evaluating the AD9235.
Documentation & Resources
AN-905: VisualAnalog™ Converter Evaluation Tool Version 1.0 User Manual8/18/2020
AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B)5/12/2015985 kB
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)2/14/2015227 K
AN-282: Fundamentals of Sampled Data Systems2/14/20152131 kB
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)2/14/2015291K
AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (Rev. 0)2/14/2015203 kB
AN-935: Designing an ADC Transformer-Coupled Front End (Rev. 0)2/14/2015363 kB
AN-742: Frequency Domain Response of Switched-Capacitor ADCs (Rev. C)2/14/2015427 K
AN-345: Grounding for Low-and-High-Frequency Circuits2/14/2015455 kB
AN-1142: Techniques for High Speed ADC PCB Layout (Rev. 0)2/2/2012392 kB
AN-737: How ADIsimADC Models an ADC (Rev. B)11/9/2007373 kB
AN-807: Multicarrier WCDMA Feasibility (Rev. 0)11/9/2007969 kB
AN-808: Multicarrier CDMA2000 Feasibility (Rev. 0)11/9/20071535 kB
AN-803: Pin Compatible High Speed ADCs Simplify Design Tasks (Rev. 0)11/29/2006356 kB
AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated (Rev. 0)12/14/2004370K
AN-741: Little Known Characteristics of Phase Noise (Rev. 0)11/29/20041679 kB
Designing Power Supplies for High Speed ADC2/1/2012
Matching An ADC To A Transformer7/13/2007
Ask The Application Engineer—36: Wideband A/D Converter Front-End Design Considerations II: Amplifier-or Transformer Drive for the ADC?2/1/2007 Analog Dialogue
Which ADC Architecture Is Right for Your Application?6/1/2005 Analog Dialogue
Correlating High-Speed ADC Performance to Multicarrier 3G Requirements6/1/2003
DNL and Some of its Effects on Converter Performance6/1/2001
Tools & Simulations
AD9235 IBIS Models
For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.
AD9235 Companion Parts
Recommended ADC Drivers
Recommended Clock Drivers
Recommended External Reference
- For improved thermal drift and gain accuracy: ADR130.
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