ADF4382A
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ADF4382A

2.87GHz to 21GHz Fractional-N PLL/VCO for High Performance Converter Clocking Applications

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2.87GHz to 21GHz Fractional-N PLL/VCO for High Performance Converter Clocking Applications

Info : RECOMMENDED FOR NEW DESIGNS tooltip
Info : RECOMMENDED FOR NEW DESIGNS tooltip
Part Details
Part Models 2
1ku List Price Starting From $160.50
Features
  • Fundamental output frequency range: 11.5 GHz to 21 GHz
  • Divide by 2 output frequency range: 5.75 GHz to 10.5 GHz
  • Divide by 4 output frequency range: 2.875 GHz to 5.25 GHz
  • Integrated RMS jitter at 20 GHz = 20 fs (integration bandwidth: 100 Hz to 100 MHz)
  • Integrated RMS jitter at 20 GHz = 31 fs (ADC SNR method)
  • VCO autocalibration time < 100 μs
  • Phase noise floor: −156 dBc/Hz at 20 GHz
  • PLL specifications
    • −239 dBc/Hz: normalized in-band phase noise floor
    • −287 dBc/Hz: normalized 1/f phase noise floor
    • 625 MHz maximum phase/frequency detector input frequency
    • 4.5 GHz reference input frequency
    • Typical spurious fPFD: −90 dBc
  • Reference to output delay specifications
  • Propagation delay temperature coefficient: 0.06 ps/°C
  • Adjustment step size: <1 ps
  • Multichip output phase alignment
  • 3.3 V and 5 V power suppliesADIsimPLL loop filter design tool support
  • 7 mm × 7 mm, 48-terminal LGA
  • −40°C to +105°C operating temperature
Additional Details
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The ADF4382A is a high performance, ultralow jitter, fractional-N phased-locked loop (PLL) with an integrated voltage controlled oscillator (VCO) ideally suited for local oscillator (LO) generation for 5G applications or data converter clock applications. The high performance PLL has a figure of merit of −239 dBc/Hz, low 1/f noise and high PFD frequency of 625 MHz in integer mode that can achieve ultralow in-band noise and integrated jitter. The ADF4382A can generate frequencies in a fundamental octave range of 11.5 GHz to 21 GHz, thereby eliminating the need for subharmonic filters. The divide by 2 and divide by 4 output dividers on the ADF4382A allow frequencies to be generated from 5.75 GHz to 10.5 GHz and 2.875 GHz to 5.25 GHz, respectively.

For multiple data converter clock applications, the ADF4382A automatically aligns its output to the input reference edge by including the output divider in the PLL feedback loop. For applications that require deterministic delay or delay adjustment capability, a programmable reference to output delay with <1 ps resolution is provided. The reference to output delay matching across multiple devices and over temperature allows predictable and precise multichip clock and system reference (SYSREF) alignment.

The simplicity of the ADF4382A block diagram eases development time with a simplified serial peripheral interface (SPI) register map, repeatable multichip clock alignment, and limiting unwanted clock spurs by allowing off-chip SYSREF generation.

Applications

  • High performance data converter clocking
  • Wireless infrastructure (MC-GSM, 5G, 6G)
  • Test and measurement
Part Models 2
1ku List Price Starting From $160.50

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Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
ADF4382ABCCZ
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  • HTML
ADF4382ABCCZ-RL7
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Software & Part Ecosystem

Software & Part Ecosystem

Evaluation Kit

Evaluation Kits 1

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EVAL-ADF4382A

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EVAL-ADF4382A

Features and Benefits

  • Self-contained evaluation board, including the ADF4382A frequency synthesizer with integrated VCO, loop filter, USB interface, on-board reference oscillator, propagation delay calibration paths, and voltage regulators
  • Windows®-based software allows control of synthesizer functions from a PC
  • Externally powered by 6 V

Product Detail

The EV-ADF4382ASD2Z evaluates the performance of the ADF4382A frequency synthesizer with an integrated voltage-controlled oscillator (VCO) for phase-locked loops (PLLs). A photograph of the evaluation board is shown in Figure 1. The EVADF4382ASD2Z contains the ADF4382A frequency synthesizer with an integrated VCO, a USB interface, power supply connectors, on-board reference oscillator, propagation delay calibration paths, and Subminiature Version A (SMA) connectors. The outputs of the EV-ADF4382ASD2Z are AC-coupled with 50 Ω transmission lines, making these outputs suitable to drive 50 Ω impedance instruments.

The EV-ADF4382ASD2Z requires an SDP-S controller board, which is not supplied with the evaluation board kit). The SDP-S allows software programming of the EV-ADF4382ASD2Z with Analog Devices, Inc., ACE software.

Full specifications for the ADF4382A frequency synthesizer are available in the ADF4382A data sheet, which must be consulted in conjunction with this user guide when working with the EVADF4382ASD2Z.

Evaluation Kits1

Tools & Simulations

Tools & Simulations 3

LTspice® is a powerful, fast and free simulation software, schematic capture and waveform viewer with enhancements and models for improving the simulation of analog circuits.

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