AD4632-20

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20-Bit, 2MSPS/500kSPS Dual-Channel SAR ADCs

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ADI公司所提供的资料均视为准确、可靠。但本公司不为用户在应用过程中侵犯任何专利权或第三方权利承担任何责任。技术指标的修改不再另行通知。本公司既没有含蓄的允许,也不允许借用ADI公司的专利或专利权的名义。本文出现的商标和注册商标所有权分别属于相应的公司。

概述

  • High performance
    • Throughput: 2MSPS (AD4630-20) or 500kSPS (AD4632-20) per channel maximum
    • INL: ±0.8ppm typical from −40°C to +125°C
    • SNR: 105.7dB typical
    • THD: −127dB typical
    • NSD: −166dBFS/Hz typical
  • Low power
    • 15mW per channel at 2MSPS
    • 5mW per channel at 500kSPS
    • 1.5mW per channel at 10kSPS
  • Easy Drive features reduce system complexity
    • Low 0.6μA input current for DC inputs at 2MSPS
    • Wide input common-mode range: −(1/128) × VREF to +(129/128) × VREF
  • Flexible external reference voltage range: 4.096V to 5V
    • Accurate integrated reference buffer with 2μF bypass capacitor
  • Programmable block averaging filter with up to 216 decimation
    • Extended sample resolution to 30 bits
    • Overrange and synchronization bits
  • Flexi-SPI digital interface
    • 1, 2, or 4 SDO lanes per channel allows slower SCK
    • Echo clock mode simplifies use of digital isolator
    • Compatible with 1.2V to 1.8V logic
  • 7 mm × 7 mm 64-Ball CSP_BGA package with internal supply and reference capacitors to help reduce system footprint
AD4632-20
20-Bit, 2MSPS/500kSPS Dual-Channel SAR ADCs
AD4630-20-AD4632-20 Functional Block Diagram AD4630-20-AD4632-20 Pin Configuration AD4630-20 Chip Illustration
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