- Highly integrated transceiver with single-channel transmitter and dual-channel receivers
- Frequency range of 30 MHz to 6000 MHz
- Transmitter and receiver bandwidth up to 40 MHz
- Fully integrated, fractional-N, RF synthesizers
- LVDS and CSSI
- Low power monitor and sleep modes
- Multichip synchronization capabilities
- Dynamic profile switching for dynamic data rates and sample rates
- Fully programmable via a 4-wire SPI
- 12 mm × 12 mm, 196-ball CSP_BGA
The ADRV9003 is a highly integrated, RF transceiver that has a single-channel transmitter, dual-channel receivers, integrated synthesizers, and digital signal processing functions.
The IC delivers a versatile combination of high performance and low power consumption required by battery powered radio equipment and can operate in both FDD and TDD modes. The ADRV9003 operates from 30 MHz to 6000 MHz and covers the UHF, VHF, licensed, and unlicensed cellular bands, and industrial, scientific, and medical (ISM) bands. The IC can support both narrow-band and wideband standards up to 40 MHz bandwidth on both receive and transmit.
The transceiver consists of direct conversion signal paths with state of the art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, quadrature error correction, and programmable digital filters, which eliminate the need for these functions in the digital baseband. In addition, several auxiliary functions such as auxiliary analog-to-digital converters (ADCs), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integrated to provide additional monitoring and control capability.
The fully integrated phase-locked loops (PLLs) provide high performance, low power, fractional-N frequency synthesis for the transmitter, receiver, and clock sections. Careful design and layout techniques provide the isolation required in high performance personal radio applications.
All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count. The local oscillators (LOs) have flexible configuration options and include fast lock modes.
The transceiver includes low power sleep and monitor modes to save power and extend the battery life of portable devices while monitoring communication.
The ADRV9003 core can be powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard 4-wire serial port. Other voltage supplies are used to provide proper digital interface levels and to optimize receiver, transmitter, and auxiliary converter performance.
High data rate and low data rate interfaces are supported using configurable CMOS or low voltage differential signaling (LVDS) serial synchronous interface (SSI) choice. The ADRV9003 is packaged in a 12 mm × 12 mm, 196-ball chip scale package ball grid array (CSP_BGA).
The ADRV9002NP/W1/PCBZ and ADRV9002NP/W2/PCBZ are the recommended evaluation board for the ADRV9003 and ADRV9004 devices configured with the TES SW.
- Mission critical communications
- Very high frequency (VHF), ultrahigh frequency (UHF), and cellular to 6 GHz
- Time division duplexing (TDD) and frequency division duplexing (FDD) applications
For hardware or software support please visit EngineerZone:
Software and Hardware Selection Guide
Wideband RF Transceiver Evaluation Software
ADRV9001 Prototyping Software Wiki Page
Download the complete design file resource package including s-parameters, schematics, and bill of materials.