AD4880
PRE-RELEASEDual Channel 20-Bit, 40 MSPS, SAR ADC with Analog Front End
- Part Models
- 3
- 1ku List Price
- price unavailable
Part Details
- Integrated fully differential ADC drivers
- Wide input common-mode voltage range
- High common-mode rejection
- Single-ended to differential conversion
- Gain options include: 1.03, 1.25, 1.53, 2.03, 2.74, 4.11, and 5.77
- Integrated gain-setting resistors
- High performance
- 20-bit resolution, no missing codes
- Throughput: 40 MSPS per channel
- Conversion latency: 46.25 ns
- INL: ±5 ppm (typical), ±10 ppm (maximum)
- SNR/THD
- 92.6 dB (typical)/−110 dB (typical) at fIN = 1 kHz
- TBD dB (typical)/−TBD dB (typical) at fIN = 500 kHz
- Noise spectral density: −167.6 dBFS/Hz
- Low power
- 105 mW per channel typical at 40 MSPS
- Integrated, low-drift reference buffers and decoupling
- Integrated VCM generation
- Digital features and data interface
- Conversion result FIFO, 16K samples per channel
- Digital averaging filter with up to 210 decimation
- SPI configuration per channel
- Configurable data interface per channel
- Single lane, DDR, serial LVDS, 800 MBPS per lane
- Dual lane, DDR, serial LVDS, 400 MBPS per lane
- Single/quad lane SPI data interface
- Package
- 196-ball, 10 mm x 10 mm CSP_BGA, 0.65 mm pitch
- Integrated supply decoupling capacitors
- Operating temperature range: −40°C to +85°C
The AD4880 is a dual-channel, low noise, high speed, low distortion, 20-bit, successive approximation register (SAR) analog-to-digital converter (ADC) with integrated fully differential drivers (FDA) and gain setting resistors. Maintaining high performance (signal-to-noise and distortion (SINAD) ratio > TBD dB) at signal frequencies up to TBD kHz allows the AD4880 to service a wide variety of precision, wide bandwidth data acquisition applications.
The integration of the ADC drivers, low drift reference buffers, low dropout (LDO) regulators along with all critical decoupling capacitors greatly alleviate analog front-end design challenges. Specified performance is easier to achieve, requiring a simpler and overall smaller printed circuit board (PCB) layout.
The internal nodes of the FDA stage are accessible, which allows setting its frequency response in a flexible way, enabling filter configurations up to 3rd order by the use of external passive components without the need for an additional amplifier. The requirements for the input anti-alias filtering can be relaxed by oversampling in combination with usage of the integrated digital filters and decimation to reduce noise and lower the output data rate, for applications that do not require the lowest latency of the AD4880.
High throughput and low-latency applications can benefit from the two independent, multilane low voltage differential signaling (LVDS) interfaces. Alternatively, the load on the digital host can be eased by storing the captured data in the on-chip, 16K samples per channel first in, first out (FIFO) memory, then asynchronously accessing it via the data interfaces.
APPLICATIONS
- Digital imaging
- Cell analysis
- Spectroscopy
- High speed data acquisition
- Digital control loops, hardware in the loop
- Power quality analysis
- Source measurement units
- Nondestructive test
Documentation
Data Sheet 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD4880BBCZ | CHIP SCALE BGA | ||
| AD4880BBCZ-RL | CHIP SCALE BGA | ||
| AD4880BBCZ-RL7 | CHIP SCALE BGA |
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