AD9461:  16-Bit, 130 MSPS A/D Converter


The AD9461 is a 16-bit, monolithic, sampling analog-to-digital converter (ADC) with an on-chip track-and-hold circuit. It is optimized for performance, small size, and ease of use. The product operates up to 130 MSPS, providing superior SNR for instrumentation, medical imaging, and radar receivers employing baseband (<100 MHz) and IF frequencies.

The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are CMOS or LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances.

Optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data mode.

The AD9461 is available in a Pb-free, 100-lead, surface-mount, plastic package (100-lead TQFP/EP) specified over the industrial temperature range −40°C to +85°C.

Product Highlights

  1. True 16-bit linearity.
  2. High performance: outstanding SNR performance for baseband IFs in data acquisition, instrumentation, magnetic resonance imaging, and radar receivers.
  3. Ease of use: on-chip reference and high input impedance track-and-hold with adjustable analog input range and an output clock simplifies data capture.
  4. Packaged in a Pb-free, 100-lead TQFP/EP package.
  5. Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of clock pulse widths.
  6. OR (out-of-range) outputs indicate when the signal is beyond the selected input range.


  • MRI receivers
  • Multicarrier, multimode cellular receivers
  • Antenna array positioning
  • Power amplifier linearization
  • Broadband wireless
  • Radar
  • Infrared imaging
  • Communications instrumentation


  • 130 MSPS guaranteed sampling rate (AD9461-130)
  • 78.4 dBFS SNR with 10 MHz input
    (3.4 V p-p input, 130 MSPS)
  • 77.1 dBFS SNR / 85 dBc SFDR with 170 MHz
    input (3.4V p-p input, 130 MSPS)
  • 83 dBc SFDR with 225 MHz input
    (3.4V p-p input, 130 MSPS)
  • TBD dBFS 2-tone SFDR with 170 MHz and 170 MHz (130 MSPS)
  • 60 fsec rms jitter
  • Excellent linearity
    DNL = ±0.6 LSB typical
    INL = ±4.0 LSB typical
  • 2.0 V p-p to 4.0 V p-p differential full-scale input
  • Buffered analog inputs
  • LVDS outputs (ANSI-644 compatible) or CMOS outputs
  • Data format select (offset binary or twos complement)
  • Output clock available

Functional Block Diagram for AD9461


在直流耦合应用中驱动此ADC时,建议使用 ADA4938-1。在交流耦合应用中驱动此ADC时,建议使用 AD8352AD8375


快讯名称 内容类型 文件类型
AD9461: 16-Bit, 130 MSPS IF Sampling ADC Data Sheet (Rev 0, 05/2006) (pdf, 813 kB) 产品数据手册 PDF
AN-1142: 高速ADC PCB布局布线技巧  (pdf, 392 kB) 应用笔记 PDF
AN-1142: Techniques for High Speed ADC PCB Layout  (pdf, 392 kB) 应用笔记 PDF
AN-935: ADC变压器耦合前端设计[中文版]  (pdf, 448 kB) 应用笔记 PDF
AN-935: Designing an ADC Transformer-Coupled Front End  (pdf, 363 kB) 应用笔记 PDF
AN-905: VisualAnalog™转换器评估工具1.0版用户手册  (pdf, 2124 kB) 应用笔记 PDF
AN-905: VisualAnalog Converter Evaluation Tool Version 1.0 User Manual  (pdf, 2124 kB) 应用笔记 PDF
AN-835: 高速ADC测试和评估  (pdf, 1916 kB) 应用笔记 PDF
AN-835: Understanding High Speed ADC Testing and Evaluation  (pdf, 985 kB) 应用笔记 PDF
AN-808: Multicarrier CDMA2000 Feasibility  (pdf, 1535 kB)
The goal of this application note is to determine the feasibility of implementing a multicarrier CDMA2000 transceiver and what the major subsystem performances must be.
应用笔记 PDF
AN-808: Multicarrier CDMA2000 Feasibility  (pdf, 1535 kB)
The goal of this application note is to determine the feasibility of implementing a multicarrier CDMA2000 transceiver and what the major subsystem performances must be.
应用笔记 PDF
AN-807: 多载波WCDMA的可行性  (pdf, 969 kB) 应用笔记 PDF
AN-807: Multicarrier WCDMA Feasibility  (pdf, 969 kB) 应用笔记 PDF
AN-756: 系统采样以及时钟相位噪声和抖动的影响[中文版]  (pdf, 808 kB) 应用笔记 PDF
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter  (pdf, 291 kB) 应用笔记 PDF
AN-741: 鲜为人知的相位噪声特性  (pdf, 359 kB) 应用笔记 PDF
AN-737: 如何用ADIsimADC完成ADC建模  (pdf, 373 kB) 应用笔记 PDF
AN-737: How ADIsimADC Models an ADC  (pdf, 373 kB) 应用笔记 PDF
AN-715: 走近IBIS模型:什么是IBIS模型?它们是如何生成的?  (pdf, 370 kB) 应用笔记 PDF
AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated  (pdf, 370 kB) 应用笔记 PDF
AN-586: 高速模数转换器的LVDS数据输出[中文版]  (pdf, 307 kB)
应用笔记 PDF
AN-586: LVDS Outputs for High Speed A/D Converters  (pdf, 207 kB)
High Speed ADCs Uses LVDS (Low-Voltage Differential Signaling) to Minimize Performance Limitations In ADC Applications When Providing High Speed Data Output
应用笔记 PDF
AN-501: 孔径不确定度与ADC系统性能[中文版]  (pdf, 227 kB)
应用笔记 PDF
AN-501: Aperture Uncertainty and ADC System Performance  (pdf, 227 kB)
A Key Concern in IF Sampling is that of Aperture Uncertainty (Jitter)
应用笔记 PDF
AN-345: 低频和高频电路接地  (pdf, 823 kB)
应用笔记 PDF
AN-345: Grounding for Low-and-High-Frequency Circuits  (pdf, 455 kB)
Know Your Ground and Signal Paths for Effective Designs. Current Flow Seeks Path of Least Impedance-Not Just Resistance....
应用笔记 PDF
AN-282: 采样数据系统基本原理[中文版]  (pdf, 1559 kB) 应用笔记 PDF
AN-282: Fundamentals of Sampled Data Systems  (pdf, 2131 kB) 应用笔记 PDF
UG-173:高速ADC USB FIFO评估套件(HSC-ADC-EVALB-DCZ)  (pdf, 774 kB) 用户指导 PDF
MS-2210:高速ADC的电源设计  (pdf, 327 kB) 技术文章 PDF
ADCs Offer True 16-bit Resolution
(ECN, 5/1/2006)
产品评述 HTML
RAQs index 非常见问题解答 HTML
术语表 专业词汇表 HTML


快讯名称 内容类型 文件类型
高速ADC评估板软件及行为模型 ADIsim Design/Simulation Tools HTML
AD9461 IBIS Models IBIS 模型 HTML



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  • 针对第二奈奎斯特区的频率,推荐使用AD8352AD8375 差分驱动器。
  • 针对直流耦合应用,推荐使用ADA4938-1
推荐AD9461使用的时钟驱动器 推荐电源解决方案
  • 欲选择电压调节器产品,请使用ADIsimPower






AD9461 评估板
产品型号 描述 报价 RoHS 查看PCN/PDN 查看库存/
AD9461-LVDS/PCBZ 产品状态: 停产 Evaluation Board - - 联络ADI



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