Volume 33, Number 7, July/August, 1999 Download this article in PDF format. (83.5 KB)
Phase Locked Loops for HighFrequency Receivers and Transmitters3 The first part of this series introduced phaselocked loops (PLLs), described basic architectures and principles of operation. It also included an example of where a PLL is used in communications systems. In the second part of the series, critical performance specifications, like phase noise, reference spurs, and output leakage, were examined in detail, and their effects on system performance were considered. In this, the last part of the series, we will deal with some of the main building blocks that go to make up the PLL synthesizer. We will also compare integerN and fractionalN architectures. The series will end with a summary of VCOs currently available on the market and a listing of the Analog Devices family of synthesizers.
PLL Synthesizer basic building blocks
The heart of a synthesizer is the phase detector—or phasefrequency detector. This is where the reference frequency signal is compared with the signal fed back from the VCO output, and the resulting error signal is used to drive the loop filter and VCO. In a digital PLL (DPLL) the phase detector or phasefrequency detector is a logical element. The three most common implementations are:
Figure 1 shows one implementation of a PFD, basically consisting of two Dtype flip flops. One Q output enables a positive current source; and the other Q output enables a negative current source. Assuming that, in this design, the Dtype flip flop is positiveedge triggered, the states are these:
Figure 1. Typical PFD using Dtype flip flops. Consider now how the circuit behaves if the system is out of lock and the frequency at +IN is much higher than the frequency at IN, as exemplified in Figure 2.
Figure 2. PFD waveforms, out of frequency and phase lock. Since the frequency at +IN is much higher than that at –IN, the output spends most of its time in the high state. The first rising edge on +IN sends the output high and this is maintained until the first rising edge occurs on –IN. In a practical system this means that the output, and thus the input to the VCO, is driven higher, resulting in an increase in frequency at –IN. This is exactly what is desired. If the frequency on +IN were much lower than on –IN, the opposite effect would occur. The output at OUT would spend most of its time in the low condition. This would have the effect of driving the VCO in the negative direction and again bring the frequency at –IN much closer to that at +IN, to approach the locked condition. Figure 3 shows the waveforms when the inputs are frequencylocked and close to phaselock.
Figure 3. PFD waveforms, in frequency lock but out of phase lock. Since +IN is leading –IN, the output is a series of positive current pulses. These pulses will tend to drive the VCO so that the –IN signal become phasealigned with that on +IN. When this occurs, if there were no delay element between U3 and the CLR inputs of U1 and U2, it would be possible for the output to be in highimpedance mode, producing neither positive nor negative current pulses. This would not be a good situation. The VCO would drift until a significant phase error developed and started producing either positive or negative current pulses once again. Over a relatively long period of time, the effect of this cycling would be for the output of the charge pump to be modulated by a signal that is a subharmonic of the PFD input reference frequency. Since this could be a low frequency signal, it would not be attenuated by the loop filter and would result in very significant spurs in the VCO output spectrum, a phenomenon known as the backlash effect. The delay element between the output of U3 and the CLR inputs of U1 and U2 ensures that it does not happen. With the delay element, even when the +IN and –IN are perfectly phasealigned, there will still be a current pulse generated at the charge pump output. The duration of this delay is equal to the delay inserted at the output of U3 and is known as the antibacklash pulse width.
The Reference Counter
Figure 4. Using a reference counter in a PLL synthesizer.
The Feedback Counter, N This structure has grown as a solution to the problems inherent in using the basic dividebyN structure to feed back to the phase detector when very highfrequency outputs are required. For example, let's assume that a 900MHz output is required with 10kHz spacing. A 10MHz reference frequency might be used, with the RDivider set at 1000. Then, the Nvalue in the feedback would need to be of the order of 90,000. This would mean at least a 17bit counter capable of dealing with an input frequency of 900 MHz. To handle this range, it makes sense to precede the programmable counter with a fixed counter element to bring the very high input frequency down to a range at which standard CMOS will operate. This counter, called a prescaler, is shown in Figure 5.
Figure 5. Basic prescaler. However, using a standard prescaler introduces other complications. The system resolution is now degraded (F_{1} ´ P). This issue can be addressed by using a dualmodulus prescaler (Figure 6). It has the advantages of the standard prescaler but without any loss in system resolution. A dualmodulus prescaler is a counter whose division ratio can be switched from one value to another by an external control signal. By using the dualmodulus prescaler with an A and B counter one can still maintain output resolution of F_{1}. However, the following conditions must be met:
Figure 6. Dualmodulus prescaler
Assume that the B counter has just timed out and both counters have been reloaded with the values A and B. Let's find the number of VCO cycles necessary to get to the same state again. As long as the A counter has not timed out, the prescaler is dividing down by P+1. So, both the A and B counters will count down by 1 every time the prescaler counts (P+1) VCO cycles. This means the A counter will time out after ((P+1) ´ A) VCO cycles. At this point the prescaler is switched to dividebyP. It is also possible to say that at this time the B counter still has (BA) cycles to go before it times out. How long will it take to do this: ((BA) ´ P). The system is now back to the initial condition where we started.
The total number of VCO cycles needed for this to happen is: When using a dualmodulus prescaler, it is important to consider the lowest and highest values of N. What we really want here is the range over which it is possible to change N in discrete integer steps. Consider the expression N = A + BP. To ensure a continuous integer spacing for N, A must be in the range 0 to (P–1). Then, every time B is incremented there is enough resolution to fill in the all the integer values between BP and (B+1)P. As was already noted for the dualmodulus prescaler, B must be greater than or equal to A for the dual modulus prescaler to work. From these we can say that the smallest division ratio possible while being able to increment in discrete integer steps is:
The highest value of N is given by
In this case A_{max} and B_{max} are simply determined by the size of the A and B counters.
Now for a practical example with the ADF4111.
ADF4110 Family The building blocks discussed in the previous sections are all used in the new families of integerN synthesizers from ADI. The ADF4110 family of synthesizers consists of single devices and the ADF4210 family consists of dual versions. The block diagram for the ADF4110 is shown below. It contains the reference counter, the dualmodulus prescaler, the N counter and the PFD blocks described above. Figure 7. Block diagram for the ADF4110 family. Click for a larger image
FractionalN Synthesizers The technique was originally developed in the early 1970s.This early work was done mainly by Hewlett Packard and Racal. The technique originally went by the name of "digiphase" but it later became popularly named fractionalN. In the standard synthesizer, it is possible to divide the RF signal by an integer only. This necessitates the use of a relatively low reference frequency (determined by the system channel spacing) and results in a high value of N in the feedback. Both of these facts have a major influence on the system settling time and the system phase noise. The low reference frequency means a long settling time, and the high value of N means larger phase noise. If division by a fraction could occur in the feedback, it would be possible to use a higher reference frequency and still achieve the channel spacing. This lower fractional number would also mean lower phase noise. If fact it is possible to implement division by a fraction over a long period of time by alternately dividing by two integers (divide by 2.5 can be achieved by dividing successively by 2 and 3). So, how does one divide by X or (X + 1) (assuming that the fractional number is between these two values)? Well, the fractional part of the number can be allowed to accumulate at the reference frequency rate.
Figure 8. FractionalN synthesizer. The diagram of Figure 9 shows the timing of the FractionalN system described in Figure 8. For the purpose of this example, we have assumed a divide ratio of 4.6. The signal F_{OUT} shows 46 cycles during the time that FREF is executing 10 cycles. During the time that FREF generates its first cycle, the N counter is required to divide by 4.6. Of course, this is not possible. It divides by 4. Thus, in the first cycle, 0.6 pulses are "missing" from the counter output. This is memorized in the system using an accumulator. The accumulator uses the same code as the F Register. At the beginning of each reference cycle, the accumulator adds the F Register contents to its previously accumulated value. Thus, starting at time 0, the accumulator will keep track of the "missing" pulse fractions. In the second reference cycle, the N counter will again divide by 4. The accumulator will now add 0.6 to the 0.6 accumulated from the first Reference Cycle. This gives a value of 1.2 in the accumulator but, since it can only store values less than 1, an overflow will be generated and 0.2 kept as the accumulator contents. The overflow is used to activate the pulse removing circuit. Thus, the next pulse generated by the VCO is removed from the input to the N counter. This pulse removal has the same effect as dividing by 5 instead of 4. As shown in the diagram, the accumulator again overflows in the 4th, 5th, 7th, 9th and 10th cycles. So, in a series of 10 reference cycles there are six overflows yielding a total count of (4 ´ 4) + (6 ´ 5) = 46. This is exactly what was wanted.
Summary of VCO Manufacturers
VCOs
The Analog Devices Synthesizer Family
ADI PLL Selection Guide  February 2002 
Single/ Dual 
ADI Model  2nd Source?  Max. RF Input Frequency F_{IN} (MHz) 
Phase Noise @ 1KHz ?_{N} dBc/Hz, 200kHz PFD 
Phase Noise Frequency 
Max. Reference Oscillator Frequency F_{OSC} (MHz) 
RF Prescalers  Power Dissipation on (mA) 
Package 
Single RF  ADF4001BRU  Proprietary  165  99  200MHz  100  4.5mA  TSSOP16  
Single RF  ADF4001BCP  Proprietary  165  99  200MHz  100  4.5mA  CSP20  
Single RF  ADF4110BRU  Proprietary  550  91  540MHz  100  4.5mA  TSSOP16  
Single RF  ADF4110BCP  Proprietary  550  91  540MHz  100  4.5mA  CSP20  
Single RF  ADF4111BRU  Proprietary  1200  78  836MHz  100  4.5mA  TSSOP16  
Single RF  ADF4111BCP  Proprietary  1200  78  836MHz  100  4.5mA  CSP20  
Single RF  ADF4112BRU  Proprietary  3000  86  1750Mhz  100  8/9 16/17 32/33 64/65  6.5mA  TSSOP16 
Single RF  ADF4112BCP  Proprietary  3000  86  1750Mhz  100  8/9 16/17 32/33 64/65  6.5mA  CSP20 
Single RF  ADF4113BRU  Proprietary  3700  85  1960Mhz  100  8/9 16/17 32/33 64/65  8.5mA  TSSOP16 
Single RF  ADF4113BCP  Proprietary  3700  85  1960Mhz  100  8/9 16/17 32/33 64/65  8.5mA  CSP20 
Single RF  ADF4106BRU  Proprietary  6000  84  5800MHz  250  8/9 16/17 32/33 64/65  13mA  TSSOP16 
Single RF  ADF4106BCP  Proprietary  6000  84  5800MHz  250  8/9 16/17 32/33 64/65  13mA  CSP20 
Single RF  ADF4116BRU  LMX2306TM  550  89  540MHz  100  8/9  4.5mA  TSSOP16 
Single RF  ADF4117BRU  LMX2316TM  1200  87  900MHz  100  32/33  4.5mA  TSSOP16 
Single RF  ADF4118BRU  LMX2326TM  3000  90  900Mhz  100  32/33  6.5mA  TSSOP16 
Dual RF/IF  ADF4210BRU  Proprietary  1200  89  900MHz  115  8/9 16/17 32/33 64/65  4.5mA  TSSOP20 
Dual RF/IF  ADF4210BCP  Proprietary  1200  89  900MHz  115  8/9 16/17 32/33 64/65  4.5mA  CSP20 
Dual RF/IF  ADF4211BRU  Proprietary  2000  89  900MHz  115  8/9 16/17 32/33 64/65  7.5mA  TSSOP20 
Dual RF/IF  ADF4211BCP  Proprietary  2700  89  900MHz  115  8/9 16/17 32/33 64/65  7.5mA  CSP20 
Dual RF/IF  ADF4212BRU  Proprietary  2700  91  900MHz  115  8/9 16/17 32/33 64/65  11.5mA  TSSOP20 
Dual RF/IF  ADF4212BCP  Proprietary  2700  91  900MHz  115  8/9 16/17 32/33 64/65  11.5mA  CSP20 
Dual RF/IF  ADF4212LBRU  Proprietary  2500  91  900MHz  115  8/9 16/17 32/33 64/65  6mA  TSSOP20 
Dual RF/IF  ADF4212LBCP  Proprietary  2500  91  900MHz  115  8/9 16/17 32/33 64/65  6mA  CSP20 
Dual RF/IF  ADF4213BRU  Proprietary  3000  91  900MHz  115  8/9 16/17 32/33 64/65  13mA  TSSOP20 
Dual RF/IF  ADF4213BCP  Proprietary  3000  91  900MHz  115  8/9 16/17 32/33 64/65  13mA  CSP20 
Dual RF/IF  ADF4206BRU  LMX2337TM  550  92  540MHz  40  32/33 64/65  9.5mA  TSSOP20 
Dual RF/IF  ADF4207BRU  LMX2335TM  1100  90  900MHz  40  32/33 64/65  11mA  TSSOP20 
Dual RF/IF  ADF4208BRU  LMX2336TM  2000  89  900MHz  40  32/33 64/65  14mA  TSSOP20 
Dual RF/IF  ADF4216BRU  LMX2332TM  1200  87  900MHz  40  32/33 64/65  9mA  TSSOP20 
Dual RF/IF  ADF4217BRU  LMX2331TM  2000  88  900MHz  40  32/33 64/65  12mA  TSSOP20 
Dual RF/IF  ADF4217LBRU  LMX2331LTM  2000  88  900MHz  110  32/33 64/65  7mA  TSSOP20 
Dual RF/IF  ADF4217LBCC  LMX2331LSLB  2500  88  900MHz  110  32/33 64/65  7mA  BCC24 
Dual RF/IF  ADF4218BRU  LMX2330TM  2500  90  900MHz  40  32/33 64/65  14mA  TSSOP20 
Dual RF/IF  ADF4218LBRU  LMX2331LTM  2500  90  900MHz  110  32/33 64/65  7mA  TSSOP20 
Dual RF/IF  ADF4218LBCC  LMX2331LSLB  2500  90  900MHz  110  32/33 64/65  7mA  BCC24 
Dual RF/IF  ADF4219LBRU  LMX2370TM  3000  90  900MHz  110  32/33 64/65  7mA  TSSOP20 
Dual RF/IF  ADF4219LBCC  LMX2370SLB  3000  90  900MHz  110  32/33 64/65  7mA  BCC24 
Dual RF/IF  ADF4252BCP  Proprietary  3000  103  1740MHz  150  4/5 8/9  12mA  CSP24 
Acknowledgements
