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ADSP-21363:  HIGH-PERFORMANCE 32-BIT FLOATING-POINT SHARC PROCESSOR FOR GENERAL PURPOSE APPLICATIONS

The third generation of SHARC® Processors, which includes the ADSP-21261, ADSP-21262, ADSP-21266, ADSP-21363, ADSP-21364, ADSP-21365, and ADSP-21366 offers increased performance, audio and application-focused peripherals, and memory configurations capable of supporting surround-sound decoder algorithms. All devices are pin-compatible with each other and completely code-compatible with all prior ...More

ADSP-21363:  HIGH-PERFORMANCE 32-BIT FLOATING-POINT SHARC PROCESSOR FOR GENERAL PURPOSE APPLICATIONS

Product Description

The third generation of SHARC® Processors, which includes the ADSP-21261, ADSP-21262, ADSP-21266, ADSP-21363, ADSP-21364, ADSP-21365, and ADSP-21366 offers increased performance, audio and application-focused peripherals, and memory configurations capable of supporting surround-sound decoder algorithms. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These members of the SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications.

The ADSP-21363 offers the highest performance – 333 MHz/2 GFLOPs -- within the third generation SHARC Processor family. This level of performance makes the ADSP-21363 particularly well suited to address the increasing requirements of many general purpose signal processing applications.

Third generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Audio Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include, but are not limited to, serial ports, SPI ports and an 8-Channel asynchronous sample rate converter block.

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  • 333 MHz SIMD SHARC Core, capable of 2 GFLOPS peak performance
  • 3Mbits SRAM ; 4Mbits customer-definable ROM
  • 25 zero-overhead DMA channels
  • Digital Audio Interface (DAI) enabling user-definable access to peripherals including 8-channel asynchronous sample rate converter.
  • 16 Pulse Width Modulation (PWM) channels
  • 6 serial ports (SPORTs) supporting I2S, left-justified sample pair, and TDM modes
  • 2 SPI-compatible ports supporting master and slave modes
  • 3 full-featured timers
  • 136-ball MBGA and 144-Ld LQFP E-Pad
    package options
  • Commercial and industrial temperature ranges
  • Clock Speed (MHz): 333MHz
  • MMACs: 666
  • MFLOPs: 1998
  • On-Chip SRAM (Mbits): 3Mbit
  • Serial Ports: 6
  • Core Voltage (V): 1.2V
  • DAI: X
  • Package: CSP_BGA,LQFP-EP

Functional Block Diagram for ADSP-21363

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Model
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For detailed drawings and chemical composition please consult our  Package Site

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Temperature Range
This is the acceptable operating range of the device. The various ranges specified are as follows:
  • Commercial: 0 to +70 degrees Celsius
  • Military : -55 to +125 degrees Celsius
  • Industrial: Temperature ranges may vary by model. Please consult the datasheet for more information.
  • Automotive: -40 to +125 degrees Celsius
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*The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.
**Sample availability may be better than production availability. Please enter samples into your cart to check sample availability.