Overview
Features and Benefits
- 333MHz /1.8 GFLOPs SIMD SHARC core supporting IEEE 32-bit floating-point, 40-bit floating-point and 32-bit fixed-point data types
- 3Mbits SRAM; On-chip ROM embedded with industry-standard audio decode and post-processing algorithms available to qualified Dolby and DTS licensees only.
- Use of DTCP enabled components is restricted to DTCP technology adopters only.
- Digital Audio Interface (DAI) enabling user-definable access to peripherals including an S/PDIF Tx/Rx, 8-channel asynchronous sample rate converter, and Data Transmission Content Protection hardware accelerator
- 25 zero-overhead DMA channels
- 6 serial ports (SPORTs) supporting I2S, left-justified sample pair, and TDM modes
- 2 SPI-compatible ports supporting master and slave modes
- 16 Pulse Width Modulation (PWM) channels
- 3 full-featured timers
- 136-ball MBGA and 144-Ld LQFP E-Pad
package options - Commercial and Industrial temperature ranges
Product Details
The third generation of SHARC® Processors, which includes the ADSP-21261, ADSP-21262, ADSP-21266, ADSP-21363, ADSP-21364, ADSP-21365, and ADSP-21366, offers increased performance, audio and application-focused peripherals, and memory configurations capable of supporting surround-sound decoder algorithms. All devices are pin-compatible and completely code-compatible with all prior SHARC Processors. These members of the SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications.
The ADSP-21365 offers the highest performance – 333 MHz/1800 MFLOPs -- within the third generation SHARC Processor family. This level of performance makes the ADSP-21365 particularly well suited to address the increasing requirements of the professional and automotive audio market segments. In addition to its higher core performance, the ADSP-21365 includes additional value-added peripherals such as an S/PDIF transmitter/receiver, 8-channel asynchronous sample rate converter, and a hardware Digital Transmission Content Protection (DTCP) encryption/decryption block.
Third generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Audio Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, S/PDIF Tx/Rx, DTCP Accelerator, and an 8-Channel asynchronous sample rate converter block.
SHARC Melody Platform for the Car
The SHARC Melody platform combines high-performance processors with optimized software, thus offering complete audio solutions to the automotive marketplace. The ADSP-21365 through on-chip ROM offers industry standard audio decoder & post-processing algorithms such as:
- PCM
- Dolby Digital*
- Dolby Digital EX2*
- Dolby Pro Logic IIx*
- DTS 5.1*
- DTS ES*
- DTS Neo:6*
- DTS 96/24*
- SRS Focus*
- MPEG2 AAC LC
- MP3
- Graphic Equalizer
- Balance/Fader
- Bass Management
- Delay Management
These algorithms are factory mask-programmed ensuring that single-chip system implementations are realized and system bill of materials costs are minimized.
* License agreement required from IP holders prior to receipt of silicon samples.
Product Categories
Product Lifecycle
Not Recommended for New Designs
This designates products ADI does not recommend broadly for new designs.
Evaluation Kits (3)
Documentation & Resources
-
EE-112: Class Implementation in Analog C++11/14/2016
-
EE-356: Emulator and Evaluation Hardware Troubleshooting Guide for CCES Users (Rev. 2)2/14/2015
-
• EE-356: Associated Files
ZIP -
EE-355: Expert In-Circuit FLASH Programmer for SHARC® Processors (Rev. 1)8/20/2012
-
• EE-355: Code Example (Rev 1, 08/2012)
ZIP -
EE-243: Using the Expert DAI for SHARC® Processors (Rev. 7)7/6/2010
-
• EE-243: Code example (Rev 7, 06/2010)
ZIP -
EE-345: Boot Kernel Customization and Firmware Upgradeability on SHARC Processors® (Rev. 1)10/6/2009
-
• EE-345: Code example (Rev 1, 10/2009)
ZIP -
EE-332: Cycle Counting and Profiling (Rev. 2)8/18/2009
-
• EE-332: Code example
ZIP -
EE-322: Expert Code Generator for SHARC® Processors (Rev. 5)6/15/2009
-
• EE-322: Code Example (Rev 5, 01/2012)
ZIP -
EE-340: Connecting SHARC® and Blackfin® Processors over SPI (Rev. 1)5/8/2009
-
• EE-340: Code example
ZIP -
EE-320: Implementing an Ogg Vorbis Decoder on SHARC® Processors (Rev. 1)6/26/2008
-
• EE-320: Code example (Rev 1, 06/2008)
ZIP -
EE-323: Implementing Dynamically Loaded Software Modules (Rev. 1)3/8/2008
-
• EE-323: Associated Code
ZIP -
EE-330: Windows Vista Compatibility in VisualDSP++ 5.0 Development Tools (Rev. 1)8/31/2007
-
EE-266: Programming S/PDIF on ADSP-2136x and ADSP-21371 SHARC® Processors (Rev. 2)8/28/2007
-
• EE-266: Code example (Rev 2, 08/2007)
ZIP -
EE-231: In-Circuit Programming of an SPI Flash with SHARC® Processors (Rev. 2)8/27/2007
-
• EE-231: Code example (Rev 2, 08/2007)
ZIP -
EE-328: Migrating from ADSP-2106x/2116x to ADSP-2126x/2136x/2137x SHARC® Processors (Rev. 1)7/27/2007
-
EE-175: Emulator and Evaluation Hardware Troubleshooting Guide for VisualDSP++ Users (Rev. 14)5/21/2007
-
• EE-175: Associated Files
ZIP -
EE-56: Tips and Tricks on SHARC® EPROM and Host Boot Loader (Rev. 3)3/7/2007
-
EE-84: External Port DMA Modes of Operation for SHARC Processors (Rev. 2)3/2/2007
-
• EE-84: Code Example (Rev 2, 2/2007)
ZIP -
EE-223: In-Circuit Flash Programming on SHARC® Processors (Rev. 2)2/23/2007
-
• EE-223: Code Example (Rev 2, 02/2007)
ZIP -
EE-253: Power Bypass Decoupling of SHARC® Processors (Rev. 1)12/5/2006
-
EE-296: Using the UART Port Controller on SHARC® Processors (Rev. 2)11/22/2006
-
EE-295: Implementing Delay Lines on SHARC® Processors (Rev. 1)11/15/2006
-
• EE-295: Code Example (Rev 1, 10/2006)
ZIP -
EE-305: Designing and Debugging Systems with SHARC Processors (Rev. 1)11/15/2006
-
EE-290: Managing the Core PLL on SHARC® Processors (Rev. 5)7/12/2006
-
• EE-290: Code Example (Rev 5, 03/2012)
ZIP -
EE-277: Estimating Power for the ADSP-21362 SHARC® Processors (Rev. 1)3/9/2006
-
EE-220: Using External Memory with Third Generation SHARC® Processors and the Parallel Port (Rev. 2)8/10/2005
-
EE-270: Extended-Precision Fixed-Point Arithmetic on SIMD SHARC® Processors (Rev. 1)7/8/2005
-
• EE-270 Software Code
ZIP -
EE-264: Interfacing MultiMediaCard™ with ADSP-2126x SHARC® Processors (Rev. 1)5/6/2005
-
• EE-264 Software Code
ZIP -
EE-268: Programming Asynchronous Sample Rate Converters on ADSP-2136x SHARC® Processors (Rev. 1)4/28/2005
-
• EE-268 Software Code (04/2005)
ZIP -
EE-230: Code Overlays on the Third Generation SHARC® Family of Processors (Rev. 2)4/13/2005
-
• EE-230 Software Code (4/2005)
ZIP -
EE-267: Implementing In-Place FFTs on SISD and SIMD SHARC® Processors (Rev. 1)4/4/2005
-
• EE-267 Software Code
ZIP -
EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev. 1)2/15/2005
-
EE-260: Interfacing AD7865 Parallel ADCs to ADSP-2136x SHARC® Processors (Rev. 1)12/17/2004
-
• EE-260 Software Code
ZIP -
EE-254: Interfacing ADSP-21365 SHARC® PDAP to ADSP-BF533 Blackfin® EBIU (Rev. 1)11/18/2004
-
• EE-254 Software Code
ZIP -
EE-248: Interfacing AD7676 ADCs to ADSP-21365 SHARC® Processors (Rev. 1)10/12/2004
-
• EE-248 Software Code
ZIP -
EE-202: Using the Expert Linker for Multiprocessor LDFs (Rev. 3)9/15/2004
-
• EE-202 Software Code
ZIP -
EE-232: Configuring the Signal Routing Unit of ADSP-2126x SHARC® DSPs (Rev. 1)2/18/2004
-
EE-189: Link Port Tips & Tricks For ADSP-2106x & ADSP-2116x SHARC® DSPs10/27/2003
-
EE-191: Implementing a Glueless UART Using The SHARC® DSP SPORTs5/21/2003
-
• EE-191 Software Code
ZIP -
EE-177: SHARC® SPI Slave Booting (Rev. 3)5/2/2003
-
• EE-177: Code Example (Rev 3, 01/2007)
ZIP -
EE-68: Analog Devices JTAG Emulation Technical Reference (Rev. 10)12/20/2002
-
EE-128: DSP in C++: Calling Assembly Class Member Functions From C++9/18/2002
-
EE-69: Understanding and Using Linker Description Files on SHARC Processors (Rev. 2)9/17/2002
-
• EE-69: Code Example (Rev 2, 01/2007)
ZIP -
EE-110: A Quick Primer on ELF and DWARF File Formats5/17/2000
-
EE-104: Setting Up Streams with the VisualDSP Debugger11/5/1999
-
• EE-104 Software Code
ZIP
-
SHARC Processors: Manuals9/10/2015
-
Getting Started with SHARC2/14/2015
-
VisualDSP++® 5.0 Assembler and Preprocessor Manual (Rev. 3.4)11/15/2009
-
VisualDSP++® 5.0 Loader and Utilities Manual (Rev. 2.5)11/13/2009
-
Documentation Errata
-
VisualDSP++® 5.0 Licensing Guide (Rev. 1.4)11/13/2009
-
VisualDSP++® 5.0 Kernel (VDK) Users Guide (Rev. 3.5)11/13/2009
-
VisualDSP++® 5.0 Linker and Utilities Manual (Rev. 3.5)11/13/2009
-
VisualDSP++® 5.0 Users Guide (Rev. 3.0)12/9/2007
-
VisualDSP++® 5.0 Quick Installation Reference Card (Rev. 3.1)8/30/2007
-
VisualDSP++® 5.0 Getting Started Guide (Rev. 3.0)8/30/2007
-
Documentation Errata
-
VisualDSP++® 5.0 Product Release Bulletin (Rev. 3.0)8/30/2007
-
SHARC Processor Family9/21/2010