Overview
Features and Benefits
- 200MHz /1.2 GFLOPs SIMD SHARC core supporting IEEE 32-bit floating-point, 40-bit floating-point and 32-bit fixed-point data types
- 2Mbits SRAM; On-chip ROM embedded with industry-standard audio decode and post-processing algorithms available to qualified Dolby and DTS licensees only.
- 16-bit parallel port
- Digital Audio Interface (DAI) enabling user-definable access to peripherals including precision clock generators (PCG), input data port (IDP), and general purpose I/O
- 22 zero-overhead DMA channels
- 6 serial ports (SPORTs) supporting I2S, left-justified sample pair, and TDM modes
- SPI-compatible port supporting master and slave modes
- 3 full-featured timers
- PLL capable of a variety of multiplier ratios
- 136-ball MiniBGA and 144-lead LQFP packages
- Commercial and Industrial temperature ranges
Product Details
The third generation of SHARC Processors, which includes the ADSP-21262, ADSP-21266, ADSP-21364, and ADSP-21365, offers increased performance, audio-centric peripherals, and new memory configurations, including on-chip ROM, that are capable of supporting the latest surround-sound decoder algorithms. All devices are pin-compatible and completely code-compatible with all prior SHARC Processors. These newest members of the SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-perfomance audio applications.
Third generation SHARC Processors also integrate audio-specific peripherals designed to simplify hardware design and reduce time to market. Grouped together, and broadly named the Digital Audio Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, an Input Data Port (IDP), Precision Clock Generators (PCG), and timers. This flexibility of resource utilization combined with the ease of use of the SHARC Processor programming model allow manufacturers to leverage a single hardware design for multiple products with varying I/O requirements.
SHARC Melody Platform for the Home
The SHARC Melody platform combines high-performance processors with optimized software, thus offering complete audio solutions to Home Theater manufacturers. The ADSP-21266 is a large memory, high-performance device targeted primarily at mid- to high-end home theater systems. SHARC Melody solutions are offered through on-chip ROM containing industry standard audio decoder algorithms such as
These algorithms are factory mask-programmed ensuring that single-chip system implementations are realized and system bill of materials costs are minimized.
* License agreement required from IP holders prior to receipt of silicon samples.
Product Categories
Customers must be licensed for the appropriate Dolby and DTS technologies which exist in the on-chip ROM. Minimum annual volume requirements apply.
Please contact your local Analog Devices sales office for more information regarding the use of these products.
Product Lifecycle
Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (4)
Documentation & Resources
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EE-112: Class Implementation in Analog C++11/14/2016
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EE-356: Emulator and Evaluation Hardware Troubleshooting Guide for CCES Users (Rev. 2)2/14/2015
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• EE-356: Associated Files
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EE-355: Expert In-Circuit FLASH Programmer for SHARC® Processors (Rev. 1)8/20/2012
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• EE-355: Code Example (Rev 1, 08/2012)
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EE-243: Using the Expert DAI for SHARC® Processors (Rev. 7)7/6/2010
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• EE-243: Code example (Rev 7, 06/2010)
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EE-345: Boot Kernel Customization and Firmware Upgradeability on SHARC Processors® (Rev. 1)10/6/2009
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• EE-345: Code example (Rev 1, 10/2009)
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EE-332: Cycle Counting and Profiling (Rev. 2)8/18/2009
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• EE-332: Code example
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EE-322: Expert Code Generator for SHARC® Processors (Rev. 5)6/15/2009
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• EE-322: Code Example (Rev 5, 01/2012)
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EE-340: Connecting SHARC® and Blackfin® Processors over SPI (Rev. 1)5/8/2009
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• EE-340: Code example
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EE-323: Implementing Dynamically Loaded Software Modules (Rev. 1)3/8/2008
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• EE-323: Associated Code
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EE-330: Windows Vista Compatibility in VisualDSP++ 5.0 Development Tools (Rev. 1)8/31/2007
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EE-231: In-Circuit Programming of an SPI Flash with SHARC® Processors (Rev. 2)8/27/2007
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• EE-231: Code example (Rev 2, 08/2007)
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EE-328: Migrating from ADSP-2106x/2116x to ADSP-2126x/2136x/2137x SHARC® Processors (Rev. 1)7/27/2007
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EE-175: Emulator and Evaluation Hardware Troubleshooting Guide for VisualDSP++ Users (Rev. 14)5/21/2007
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• EE-175: Associated Files
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EE-56: Tips and Tricks on SHARC® EPROM and Host Boot Loader (Rev. 3)3/7/2007
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EE-223: In-Circuit Flash Programming on SHARC® Processors (Rev. 2)2/23/2007
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• EE-223: Code Example (Rev 2, 02/2007)
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EE-253: Power Bypass Decoupling of SHARC® Processors (Rev. 1)12/5/2006
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EE-295: Implementing Delay Lines on SHARC® Processors (Rev. 1)11/15/2006
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• EE-295: Code Example (Rev 1, 10/2006)
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EE-305: Designing and Debugging Systems with SHARC Processors (Rev. 1)11/15/2006
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EE-290: Managing the Core PLL on SHARC® Processors (Rev. 5)7/12/2006
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• EE-290: Code Example (Rev 5, 03/2012)
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EE-279: Interfacing NAND Flash Memory with ADSP-2126x SHARC® Processors (Rev. 1)11/18/2005
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• EE-279 Software Code
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EE-222: Interfacing the ADSP-21262 SHARC EZ-KIT Lite Boards to High-Speed Converter Evaluation Boards (Rev. 1)8/25/2005
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EE-220: Using External Memory with Third Generation SHARC® Processors and the Parallel Port (Rev. 2)8/10/2005
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EE-270: Extended-Precision Fixed-Point Arithmetic on SIMD SHARC® Processors (Rev. 1)7/8/2005
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• EE-270 Software Code
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EE-250: Estimating Power Dissipation for Industrial Grade ADSP-21262 SHARC® Processors (Rev. 1)5/25/2005
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EE-264: Interfacing MultiMediaCard™ with ADSP-2126x SHARC® Processors (Rev. 1)5/6/2005
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• EE-264 Software Code
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EE-230: Code Overlays on the Third Generation SHARC® Family of Processors (Rev. 2)4/13/2005
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• EE-230 Software Code (4/2005)
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EE-267: Implementing In-Place FFTs on SISD and SIMD SHARC® Processors (Rev. 1)4/4/2005
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• EE-267 Software Code
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EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev. 1)2/15/2005
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EE-255: Porting PC-Based MP3 Player Software to ADSP-21262 SHARC® Processors (Rev. 1)11/18/2004
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EE-246: Interfacing AD7276 High-Speed Data Converters to ADSP-21262 SHARC® Processors (Rev. 1)10/12/2004
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• EE-246 Software Code
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EE-202: Using the Expert Linker for Multiprocessor LDFs (Rev. 3)9/15/2004
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• EE-202 Software Code
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EE-232: Configuring the Signal Routing Unit of ADSP-2126x SHARC® DSPs (Rev. 1)2/18/2004
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EE-219: Connecting Character LCD Panels to ADSP-21262 SHARC® DSPs (Rev. 1)12/30/2003
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• EE-219 Software Code
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EE-216: Estimating Power Dissipation for ADSP-21262S SHARC® DSPs12/29/2003
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EE-189: Link Port Tips & Tricks For ADSP-2106x & ADSP-2116x SHARC® DSPs10/27/2003
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EE-208: Considering the ADSP-21262 SHARC® DSP10/9/2003
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EE-191: Implementing a Glueless UART Using The SHARC® DSP SPORTs5/21/2003
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• EE-191 Software Code
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EE-177: SHARC® SPI Slave Booting (Rev. 3)5/2/2003
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• EE-177: Code Example (Rev 3, 01/2007)
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EE-68: Analog Devices JTAG Emulation Technical Reference (Rev. 10)12/20/2002
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EE-128: DSP in C++: Calling Assembly Class Member Functions From C++9/18/2002
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EE-69: Understanding and Using Linker Description Files on SHARC Processors (Rev. 2)9/17/2002
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• EE-69: Code Example (Rev 2, 01/2007)
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EE-110: A Quick Primer on ELF and DWARF File Formats5/17/2000
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EE-104: Setting Up Streams with the VisualDSP Debugger11/5/1999
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• EE-104 Software Code
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SHARC Processors: Manuals9/10/2015
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Getting Started with SHARC2/14/2015
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ADSP-2126x SHARC® Processor Hardware Reference (Rev. 5.1)6/1/2010
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VisualDSP++® 5.0 Assembler and Preprocessor Manual (Rev. 3.4)11/15/2009
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VisualDSP++® 5.0 Loader and Utilities Manual (Rev. 2.5)11/13/2009
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Documentation Errata
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VisualDSP++® 5.0 Licensing Guide (Rev. 1.4)11/13/2009
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VisualDSP++® 5.0 Kernel (VDK) Users Guide (Rev. 3.5)11/13/2009
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VisualDSP++® 5.0 Linker and Utilities Manual (Rev. 3.5)11/13/2009
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VisualDSP++® 5.0 Users Guide (Rev. 3.0)12/9/2007
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VisualDSP++® 5.0 Quick Installation Reference Card (Rev. 3.1)8/30/2007
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VisualDSP++® 5.0 Getting Started Guide (Rev. 3.0)8/30/2007
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Documentation Errata
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VisualDSP++® 5.0 Product Release Bulletin (Rev. 3.0)8/30/2007
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SHARC Processor Family9/21/2010
Software & Systems Requirements
Software & Tools Anomaly
Software Development Tools
SigmaStudio®
Tools & Simulations
BSDL Model File
Support & Discussions
ADSP-21266 Discussions
Evaluation Boards
Pricing displayed is based on 1-piece.
Up to two boards can be purchased through Analog.com. To order more than two, please purchase through one of our listed distributors.
Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.