概览

优势和特点

  • Dual transmitters
  • Dual receivers
  • Dual input shared Observation Receiver
  • Max Rx BW: 200 MHz
  • Max Tunable Tx synthesis BW: 450 MHz
  • Max Observation Rx BW: 450MHz
  • Fully integrated fractional-N RF synthesizers
  • Fully integrated clock synthesizer
  • Multi-chip phase synchronization for RF LO and baseband clocks
  • JESD204B data path interface
  • Tuning range: 75 MHz to 6000 MHz

产品详情

The ADRV9009 is a highly integrated, radio frequency (RF) agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of the high performance and low power consumption demanded by 3G and 4G macro cell TDD base station applications.

The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The part also supports a wide-bandwidth time-shared observation path receiver for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need for these functions in the digital baseband. Several auxiliary functions such as ADCs, DACs, and GPIOs for PA and RF-front-end control are also integrated.

In addition to the autonomous AGC, it also has flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.

The received signals are digitized with a set of four high dynamic range continuous-time sigma-delta ADCs which provide inherent anti-aliasing. The combination of the direct conversion architecture, which does not suffer from out-of-band image mixing, and the lack of aliasing relaxes the requirements of the RF filters as compared to traditional IF receivers.

The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.

The observation path consists of a wide bandwidth direct-conversion receiver with state-of-the-art dynamic range.

The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.

The fully integrated phase-locked loop (PLL) provides high performance, low power fractional-N RF frequency synthesis for the transmitter and receiver signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and serial interface. Special precautions have been taken to provide the isolation demanded in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.

The high-speed JESD204B interface supports up to 12.288 Gbps lane rates resulting in two lanes per transmitter, and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths thus reducing the total number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal AGC to be invisible to the demodulator device. Details of the format are available in the device User Guide.

The core of the ADRV9009 can be powered directly from 1.3 V and 1.8 V regulators and is controlled via a standard 4 wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).

Applications

  • 3G/4G/5G TDD macro cell base stations
  • TDD active antenna systems
  • Massive MIMO
  • Phased Array Radar
  • Electronic Warfare
  • Military Communications
  • Portable test equipment

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所示报价为单片价格。所列的美国报价单仅供预算参考,指美元报价(每片美国离岸价),如有修改恕不另行通知。由于地区关税、商业税、汇率及手续费原因,国际报价可能不同。