CN0336

The circuit consists of an input current-to-voltage converter, a level shifting circuit, an ADC stage, and an output isolation stage. The 4 mA to 20 mA input signal is converted to a voltage by resistor R3. For R3 = 120Ω and an input current of 4 mA to 20 mA, the input voltage to the level shifting circuit is: 0.48 V to 2.4 V. The diode D1 is used for protection against an accidental reverse connection of the input current source.

The voltage across R3 is level shifted and attenuated by the U1A op amp that is one-half of the dual AD8606. The output of the op amp is 0.1 V to 2.4 V which matches the input range of the ADC (0 V to 2.5 V) with 100 mV headroom to maintain linearity. The buffered voltage reference (V_REF = 2.5 V) from the AD7091R ADC is used to generate the required offset. Resistor values can be modified to accommodate other popular input ranges as described later in this circuit note.

The circuit design allows single-supply operation. The minimum output voltage specification of the AD8606 is 50 mV for a 2.7 V power supply and 290 mV for 5 V power supply with 10 mA load current, over the temperature range of -40°C to +125°C. A minimum output voltage of 45 mV to 60 mV is a conservative estimate for a 3.3 V power supply, a load current less than 1 mA, and a narrower temperature range.

Considering the tolerances of the parts, the minimum output voltage (low limit of the range) is set to 100 mV to allow for a safety margin. The upper limit of the output range is set to 2.4 V in order to give 100 mV headroom for the positive swing at the ADC input. Therefore, the nominal output voltage range of the input op amp is 0.1 V to 2.4 V.

The second half of the AD8606 (U1B) is used to buffer the internal 2.5 V voltage reference of the AD7091R (U3) ADC.

The AD8606 is chosen for this application because of its low offset voltage (65 μV maximum), low bias current (1 pA maximum) and low noise (12 nV/√Hz maximum). Power dissipation is only 9.2 mW on a 3.3 V supply.

A single-pole RC filter (R2/C11) follows the op amp output stage to reduce the out-of-band noise. The cutoff frequency of the RC filter is set to 664 kHz. An optional filter (R1/C10) can be added to reduce the filter cutoff frequency even further in case of low frequency industrial noise. In such case, the sampling rate of the AD7091R can be reduced because of the lower signal bandwidth.

The AD7091R 12-bit 1 MSPS SAR ADC is chosen because of its ultralow power 349 μA at 3.3 V (1.2 mW) which is significantly lower than any competitive ADC currently available in the market. The AD7091R also contains an internal 2.5 V reference with ±4.5 ppm/oC typical drift. The input bandwidth is 7.5 MHz, and the high speed serial interface is SPI compatible. The AD7091R is available in a small footprint 10-lead MSOP.

The total power dissipation of the circuit (excluding the ADuM5401 isolator) is approximately 10.4 mW when operating on a 3.3 V supply. Galvanic isolation is provided by the ADuM5401 (C-Grade) quad channel digital isolator. In addition to the isolated output data, the ADuM5401 also provides isolated +3.3 V for the circuit. The ADuM5401 is not required for normal circuit operation unless isolation is needed. The ADuM5401 quad-channel, 2.5 kV isolators with integrated dc-to-dc converter, is available in a small 16-lead SOIC. Power dissipation of the ADuM5401 with a 7 MHz clock is approximately 140 mW.

The AD7091R requires a 50 MHz serial clock (SCLK) to achieve a 1 MSPS sampling rate. However, the ADuM5401 (C-grade) isolator has a maximum data rate of 25 Mbps that corresponds to a maximum serial clock frequency of 12.5 MHz. In addition, the SPI port requires that the trailing edge of the SCLK clock the output data into the processor, therefore the total round-trip propagation delay through the ADuM5401 (120 ns maximum) limits the upper clock frequency to 1/120 ns = 8.3 MHz.

Even though the AD7091R is a 12-bit ADC, the serial data is formatted into a 16-bit word to be compatible with the processor serial port requirements. The sampling period, TS, therefore consists of the AD7091R 650 ns conversion time plus 58 ns (extra time required from data sheet, t₁ delay + t_QUIET delay) plus 16 clock cycles for the SPI interface data transfer.

T_S = 650 ns + 58 ns + 16 × 120 ns = 2628 ns
f_S = 1/T_S = 1/2628 ns = 380 kSPS

In order to provide a safety margin, a maximum SCLK of 7 MHz and a maximum sampling rate of 300 kSPS is recommended. The digital SPI interface can be connected to the microprocessor evaluation board using the 12-pin, Pmod-compatible connector (Digilent Pmod Specifications).

Circuit Design

The circuit shown in Figure 2 provides the proper gain and level shifting to shift the 0.48 V to 2.4 V signal to the ADC input range of 0.1 V to 2.4 V.

The transfer function is obtained from the superposition principle.

Calculation of the Gain and the Resistor Values

The gain of the circuit is:

In case of an input range from 0 mA to 20 mA, the circuit does not need level shifting, and the op amp operates as follower. Then, the voltage drop on R3 must not exceed the upper limit (2.4 V) of the output range, and can be calculated from the equation:

Resistors R4, R5 and R6 can now be calculated from Equations 7 and 9, if a value to one of them is given. For example if R5 = 1000 Ω, then R4 = 5,263 Ω, and R6 = 125,310 Ω.

In the actual circuit the nearest available standard resistor values were chosen for R4 and R6. The values selected were R4 = 5.11kΩ and R6 = 124 kΩ.

If these values are chosen carefully, the overall error due to substituting standard value resistors can be made less than a few percent. However, Equation 1 should be used to re-calculate the U1A op amp output for 4 mA and 20 mA input currents to ensure that the required headroom is preserved.

The absolute accuracy in this type of circuit is primarily determined by the resistors, and therefore gain and offset calibration is required to remove the error due to standard value substitution and resistor tolerances.

Effect of Resistor Temperature Coefficients on Overall Error

Equation 1 shows that the output voltage is a function of four resistors: R3, R4, R5, and R6. The sensitivity of the full-scale output voltage at TP1 to small changes in each of the four resistors was calculated using a simulation program. The input current to the circuit was 20 mA. The individual sensitivities calculated were S_R3 = 1.2, S_R4 = 0.01, S_R5 = 0.00, S_R6 = 0.01. Assuming the individual temperature coefficients combine in a root-sum-square (rss) manner, then the overall full-scale drift using a 25 ppm/°C resistor for R3 and 100 ppm/°C resistors for R4, R5, and R6 is approximately:

The full-scale drift of 30 ppm/°C corresponds to 0.003% FSR/°C.

Effect of Active Component Temperature Coefficients on Overall Error

The dc offsets of the AD8606 op amps and the AD7091R ADC are eliminated by the calibration procedure.

The offset drift of the ADC AD7091R internal reference is 4.5 ppm/°C typical and 25 ppm/°C maximum.

The offset drift of the AD8606 op amp is 1 μV/°C typical and 4.5 μV/°C maximum.

The error due to the input offset of the U1A AD8606 is referenced to the input voltage range of 2.4 V – 0.48 V = 1.92 V, and is therefore 2.3 ppm/°C. The error due to the U1B reference buffer is referenced to 2.5 V and is also approximately 2 ppm/°C.

The total drift error is summarized in Table 1. These errors do not include the ±1 LSB integral nonlinearity error of the AD7091R.

Test Data Before and After Two-Point Calibration

To perform the two-point calibration, 4 mA is first applied to the input, and the ADC output code is recorded as Code_1. Then 20 mA is applied to the input, and the ADC output code is recorded as Code_2. The gain factor is calculated by

The input current can now be calculated corresponding to any output code, Code_x, using the equation:

The error before calibration is obtained by comparing the ideal transfer function calculated using the nominal values of the components, and real circuit transfer function without calibration. The tested circuits have been built with resistors having ±1% tolerance. The test results do not include temperature changes.

The graph in Figure 3 shows test results for percent error (FSR) before and after calibration at ambient temperature. As it is shown, the maximum error before calibration is about 0.25% FSR. After calibration, the error decreases to ±0.02% FSR, which approximately corresponds to 1 LSB error of the ADC.

PCB Layout Considerations

In any circuit where accuracy is crucial, it is important to consider the power supply and ground return layout on the board. The PCB should isolate the digital and analog sections as much as possible. The PCB for this system was constructed in a simple 2-layer stack up, but 4-layer stack up gives better EMS. See the MT-031 Tutorial for information on layout and grounding and the MT-101 Tutorial for information on decoupling techniques. Decouple the power supply to the AD8606 with 10 μF and 0.1 μF capacitors to properly suppress noise and reduce ripple. Place the capacitors as close to the device as possible with the low ESR value, 0.1 μF capacitor. Ceramic capacitors are advised for all high frequency decoupling. Power supply lines must have as large trace width as possible to provide low impedance path and reduce glitch effects on the supply line. The ADuM5401 isoPower integrated dc-to-dc converter requires power supply bypassing at the input and output supply pins. Note that low ESR bypass capacitors are required between Pin 1 and Pin 2 and between Pin 15 and Pin 16, as close to the chip pads as possible.

To suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. The recommended capacitor values are 0.1 μF and 10 μF for V_DD1 and V_ISO. The smaller capacitor must have a low ESR; for example, use of a ceramic capacitor is advised. The total lead length between the ends of the low ESR capacitor and the input power supply pin must not exceed 2 mm. Installing the bypass capacitor with traces more than 2 mm in length may result in data corruption. Consider bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 unless both common ground pins are connected together close to the package. For more information, see the ADuM5401 data sheet.

A complete documentation package including schematics, board layout, and bill of materials (BOM) can be found at www.analog.com/CN0336-DesignSupport.

High Voltage Capability

This PCB is designed in adherence with 2500 V basic insulation practices. High voltage testing beyond 2500 V is not recommended. Appropriate care must be taken when using this evaluation board at high voltages, and the PCB should not be relied on for safety functions because it has not been high potential tested (also known as hipot tested or dielectric withstanding voltage tested) or certified for safety.