Dynamically adjust Xilinx FPGA Transceiver power supply 1V±0.25%

May 30 2018

Analog Devices Guneet Chadha demos how an output voltage of a power supply (1V) to an FPGA core or I/O (eg: high speed Transceiver) can remain within tight tolerances (0.25%) using Power System Management. Also shown, “how to margin” a power supply.

For more information visit analog.com/fpga

Dynamically adjust Xilinx FPGA Transceiver power supply 1V±0.25%

May 30 2018
Analog Devices Guneet Chadha demos how an output voltage of a power supply (1V) to an FPGA core or I/O (eg: high speed Transceiver) can remain within tight tolerances (0.25%) using Power System Management. Also shown, “how to margin” a power supply.
For more information visit analog.com/fpga
modal bookmark icon

{{modalTitle}}

modal close icon

{{modalDescription}}

{{dropdownTitle}}

input down arrow
  • {{defaultSelectedText}}
    • {{#each projectNames}}
  • {{name}}
    • {{/each}} {{#if newProjectText}}
  • plus icon {{newProjectText}}
    • {{/if}}
{{#if toggleButtonDescription}}
{{toggleButtonDescription}}
{{/if}} {{#if newProjectTitle}}

{{newProjectTitle}}

{{projectNameErrorText}}

{{/if}}