Features and Benefits
- Blackfin® Processor Core with up to 600Mhz (1200 MMACS) performance
- Lockbox™ Secure Technology: Hardware-enabled security for code and content protection.
- Connectivity: High Speed USB OTG, UARTs, SPORTs, SPI, TWI, and CAN
- Human Interface: 32-bit Up/Down counter/Thumbwheel interface, 8x8 Keypad interface
- Two independent DMA controllers
- Expansion: SD/SDIO and ATAPI-6 Controllers
- Multimedia: 8/16-bit Parallel Peripheral Controller with Pixel Compositor hardware accelerator
- Synchronous interface for DDR or Mobile DDR connectivity (See data sheet ordering guide for specific product information)
- Asynchronous Memory interface for SRAM, EEPROM, NAND/NOR, Flash connectivity
The ADSP-BF542 processors were specifically designed to meet the needs of convergent multimedia applications where system performance and cost are essential ingredients. The integration of multimedia, human interface, and connectivity peripherals combined with increased system bandwidth and on-chip memory provides customers a platform to design the most demanding applications. For applications that require additional external memory, the ADSP-BF542 family provides product variants specifically designed to interface to either Standard DDR1 or 1.8V Low-Power DDR memory devices.
IP protection has become a necessary part of today’s embedded applications. The ADSP-BF54x provides a security scheme that balances flexibility and upgradeability with performance through the inclusion of a firmware based solution including OTP memory to enable users to implement private keys for secure access to program code.
The ADSP-BF542 provides peripheral flexibility to complement its high performance processing. These rich system level peripherals are well suited for Industrial multimedia applications where multiple standards are prevalent and system performance is required.
For human interface capability, the ADSP-BF542 provides a 32-bit up/down counter that can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumb wheels. An 8x8 Keypad interface is also included.
To enhance connectivity a USB 2.0 High-Speed On-the-Go (HS USB OTG) with Integrated PHY has been integrated along with standard serial connections provided by multiple on-chip SPORT, SPI, UART, TWI, and CAN interfaces to provide glue-less interfaces to multiple off chip devices including consumer and communication products, Bluetooth, and other application specific interfaces. This level of integration is perfect for the emerging and constantly changing products and standards in convergent multimedia applications.
For interfacing off chip to storage media including hard drives, CD/DVD-drives, and NAND Flash products, the ADSP-BF542 has implemented a SD/SDIO controller, ATAPI-6 controller, and an 8/16-bit NAND flash controller.
Many multimedia enhancements have also been included on the ADSP-BF542 to offload processor MIPS through hardware integration, expand LCD capabilities, and shorten customer development time. A Hardware acceleration block, the Pixel Compositor, has been developed to execute overlay, color conversion and alpha blending. This block significantly reduces processor core overhead associated with software RGB-YUV color conversion and alpha blending.
Product Lifecycle Production
At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
Evaluation Kits (3)
The Analog Devices ICE-1000 and ICE-2000 emulators facilitate the creation, test, and debug of advanced applications on Analog Devices Processors and DSPs. Working in tandem with the CrossCore® Embedded Studio development environment, these emulators provide state-of-the-art support for all JTAG-compliant Analog Devices processors.
New debug feature added for the ICE-1000/ICE-2000:
- Coresight Serial Wire Debug (SWD)
Features & Benefits
- JTAG/SWD support for Blackfin, Blackfin+, SHARC and multi-core SHARC+ with ARM
- Plug-n-Play, USB 2.0 compliant
- USB bus-powered device
- Windows® 8.1, Window 7 compatible
- Multiple processor I/O voltage support: 1.8V, 2.5V, and 3.3V
- Multiprocessor support
- JTAG/SWD clock operation of 5 MHz on the ICE-1000
- JTAG/SWD clock operation up to 46 MHZ on the ICE-2000
- Multi-colored LED for enhanced status indication
- Software controlled target reset to support remote debug
EMULATOR-USB & HP USB ICE
Analog Devices’ cost-effective Universal Serial Bus (USB)-based emulator and High performance (HP) Universal Serial Bus (USB)-based emulator each provide an easy, portable, non-intrusive, target-based debugging solution for Analog Devices JTAG processors and DSPs. These powerful USB-based emulators perform a wide range of emulation functions, including single-step and full speed execution with pre-defined breakpoints, and viewing and/or altering of register and memory contents. With the ability to automatically detect and support multiple I/O voltages, the USB and HP USB emulators enable users to communicate with all of the Analog Devices JTAG processors and DSPs using either a full speed USB 1.1 or high speed USB 2.0 port on the host PC. Applications and data can easily and rapidly be tested and transferred between the emulators and the separately available VisualDSP++ development and debugging environment(sold separately).
The plug-and-play architecture of USB allows the emulators to be automatically detected and configured by the host operating system. It can also be connected to and disconnected from the host without opening the PC or turning off the power to the PC. A 3-meter cable is included to connect the emulators to the host PC, thus providing abundant accessibility to hard to reach targets.
The HP USB-based emulator also supports the Background
Telemetry Channel (BTC), a non-intrusive method
for exchanging data between the host and target
application without affecting the target system's
Part Number: ADZS-USB-ICE
High Performance USB-Based Emulator
Part Number: ADZS-HPUSB-ICE
Tel: 1-800-ANALOGD (262-5643)
For additional information, contact your local Analog Devices Sales Office or Distributor.
Features & Benefits
- Full speed USB 1.1 interface enabling download speeds of up to 150 KB/Sec (ADZS-USB-ICE) or High speed USB 2.0 interface enabling download speeds of up to 1.5MB/sec (ADZS-HPUSB-ICE)
- Background Telemetry Channel (BTC) support enabling non-intrusive data exchange at up to 2.0 MB/sec (ADZS-HPUSB-ICE only)
- 1.8V, 2.5V, and 3.3V compliant and tolerant
- Support for all ADI JTAG processors and DSPs
- 5V tolerant and 3.3V compliant for 5V processors and DSPs
- Multiprocessor support
- 14-pin JTAG connector
- 3-meter USB cable for difficult-to-reach targets
The ADSP-BF548 EZ-KIT Lite® provides developers with a cost-effective method for initial evaluation of the ADSP-BF54x Blackfin® Processors via a USB-based, PC-hosted tool set. With this EZ-KIT Lite, users can learn more about the Analog Devices (ADI) ADSP-BF548 hardware and software development, and quickly prototype a wide range of applications.
The EZ-KIT Lite includes an ADSP-BF548 Blackfin Processor desktop evaluation board along with an evaluation suite of the VisualDSP++® development and debugging environment, including the C/C++ compiler, assembler, and linker. The evaluation suite of VisualDSP++ is designed to be used with the EZ-KIT Lite only.
The EZ-KIT Lite ships with a 4x4 Keypad, Optical Thumbwheel, QVGA Touch Screen LCD and a 40 Gigabyte Hard Drive.
Part number: ADZS-BF548-EZLITE
CROSSCORE® Tools Support
Features & Benefits
- ADSP-BF548 Processor: 400 Ball mBGA, 600MHz; 25 MHz CLKIN oscillator
- DDR SDRAM: 64 MB (8M x 16) Micron MT46V32M16
- BURST Flash: 16 MB Numonyx PC28F128P33T85A
- NAND Flash: 2 Gb Numonyx NAND02
- SPI Flash: 16 Mbit Numonyx M25P16
- Hard Drive: Toshiba MK4032GAX 40GB 2.5” drive
- AC’97 CODEC: AD1980 5.1 Surround Codec
- Keypad: ACT Components, ACT-07-30008-000-R 4x4 Keypad assembly
- Thumbwheel: CTS Corp 290UAB0R201B2, Rotary Encoder
- UART: ADM3202 RS-232 line driver/receiver; DB9 female connector
- USB Debug Agent and JTAG Header
- Connectors: HS USB OTG; SD Memory; CAN (2); HOST; Expansion Interface (3); STAMP Interface (7)
Documentation & Resources
EE-112: Class Implementation in Analog C++11/14/2016
EE-213: Host Communication via the Asynchronous Memory Interface for Blackfin® Processors (Rev. 2)2/14/2015
EE-350: Seamlessly Interfacing MEMS Microphones with Blackfin Processors (Rev. 1)8/27/2010
EE-335: Interfacing SD Cards with Blackfin Processors (Rev. 1)3/4/2010
EE-347: Formatted Print to a UART Terminal with Blackfin® Processors (Rev. 3)2/2/2010
EE-339: Using External Switching Regulators with Blackfin® Processors (Rev. 1)8/18/2009
EE-331: UART Enhancements on ADSP-BF54x Blackfin® Processors (Rev. 1)8/18/2009
EE-326: Blackfin® Processor and SDRAM Technology (Rev. 2)8/18/2009
EE-271: Using Cache Memory on Blackfin® Processors (Rev. 2)8/18/2009
EE-340: Connecting SHARC® and Blackfin® Processors over SPI (Rev. 1)5/8/2009
EE-337: Host DMA Port on ADSP-BF52x and ADSP-BF54x Blackfin® Processors (Rev. 1)5/8/2009
EE-336: Putting ADSP-BF54x Blackfin® Processor Booting into Practice (Rev. 1)5/8/2009
EE-301: Video Templates for Developing Multimedia Applications on Blackfin® Processors (Rev. 1)5/8/2009
EE-312: Building Complex VDK/LwIP Applications Using Blackfin® Processors (Rev. 2)10/8/2008
EE-344: Using the NAND Flash Controller on Blackfin Processors (Rev. 1)10/7/2008
EE-281: Hardware Design Checklist for the Blackfin® Processors (Rev. 2)7/7/2008
EE-341: Expert Pin Multiplexing Plug-in for Blackfin® Processors (Rev. 3)5/18/2008
EE-334: Using Blackfin® Processor Hibernate State for Low Standby Power (Rev. 1)5/17/2008
EE-204: Blackfin® Processor SCCB Software Interface for Configuring I2C® Slave Devices (Rev. 2)3/26/2008
EE-333: Interfacing Blackfin® Processors to Winbond W25X16 SPI Flash Devices (Rev. 1)3/25/2008
EE-323: Implementing Dynamically Loaded Software Modules (Rev. 1)3/8/2008
EE-330: Windows Vista Compatibility in VisualDSP++ 5.0 Development Tools (Rev. 1)8/31/2007
EE-185: Fast Floating-Point Arithmetic Emulation on Blackfin® Processors (Rev. 4)8/28/2007
EE-325: Interfacing Atmel Fingerprint Sensor AT77C104B with Blackfin® Processors (Rev. 1)8/20/2007
EE-324: System Optimization Techniques for Blackfin® Processors (Rev. 1)7/12/2007
EE-294: Energy-Aware Programming on Blackfin Processors (Rev. 1)6/27/2007
EE-175: Emulator and Evaluation Hardware Troubleshooting Guide for VisualDSP++ Users (Rev. 14)5/21/2007
EE-311: VisualDSP++® Flash Programmer API for Blackfin® Processors (Rev. 1)12/15/2006
EE-307: Blackfin® Processor Troubleshooting Tips Using VisualDSP++® Tools (Rev. 1)12/14/2006
EE-308: Estimating and Optimizing Booting Time for Blackfin® Processors (Rev. 1)12/13/2006
EE-309: Power Mode Transition Times of Blackfin® Processors (Rev. 1)12/6/2006
EE-306: PGO Linker - A Code Layout Tool for Blackfin Processors (Rev. 1)12/5/2006
EE-304: Using the Blackfin® Processor SPORT to Emulate a SPI Interface (Rev. 1)11/15/2006
EE-303: Using VisualDSP++® Thread-Safe Libraries with a Third-Party RTOS (Rev. 1)11/15/2006
EE-302: Interfacing ADSP-BF53x Blackfin® Processors to NAND FLASH Memory (Rev. 1)11/15/2006
EE-276: Video Framework Considerations for Image Processing on Blackfin® Processors (Rev. 1)11/8/2005
EE-269: A Beginner’s Guide to Ethernet 802.3 (Rev. 1)6/7/2005
EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev. 1)2/15/2005
EE-257: A Boot Compression/Decompression Algorithm for Blackfin® Processors (Rev. 1)12/16/2004
EE-236: Real-Time Solutions Using Mixed-Signal Front-End Devices with the Blackfin® Processor (Rev. 1)7/21/2004
EE-234: Interfacing T1/E1 Transceivers/Framers to Blackfin® Processors via the Serial Port (Rev. 1)7/21/2004
EE-235: An Introduction to Scripting in VisualDSP++® (Rev. 1)5/19/2004
EE-183: Rational Sample Rate Conversion with Blackfin® Processors (Rev. 5)10/30/2003
EE-197: ADSP-BF531/532/533 Blackfin® Processor Multi-cycle Instructions and Latencies10/8/2003
EE-192: Using C To Create Interrupt-Driven Systems On Blackfin® Processors5/30/2003
EE-68: Analog Devices JTAG Emulation Technical Reference (Rev. 10)12/20/2002
EE-149: Tuning C Source Code for the Blackfin® Processor Compiler12/16/2002
AN-336A: Image Compression: Spelling Out the Options10/15/2002
AN-336B: JPEG Compression10/15/2002
EE-128: DSP in C++: Calling Assembly Class Member Functions From C++9/18/2002
EE-110: A Quick Primer on ELF and DWARF File Formats5/17/2000
EE-104: Setting Up Streams with the VisualDSP Debugger11/5/1999
VisualDSP++® 5.0 Assembler and Preprocessor Manual (Rev. 3.4)11/15/2009
VisualDSP++® 5.0 C/C++ Compiler and Library Manual for Blackfin Processors (Rev. 5.4)11/13/2009
VisualDSP++® 5.0 Loader and Utilities Manual (Rev. 2.5)11/13/2009
VisualDSP++® 5.0 Device Drivers and System Services Manual for Blackfin Processors (Rev. 4.3)11/13/2009
VisualDSP++® 5.0 Licensing Guide (Rev. 1.4)11/13/2009
VisualDSP++® 5.0 Kernel (VDK) Users Guide (Rev. 3.5)11/13/2009
VisualDSP++® 5.0 Linker and Utilities Manual (Rev. 3.5)11/13/2009
VisualDSP++® 5.0 Users Guide (Rev. 3.0)12/9/2007
VisualDSP++® 5.0 Quick Installation Reference Card (Rev. 3.1)8/30/2007
VisualDSP++® 5.0 Getting Started Guide (Rev. 3.0)8/30/2007
VisualDSP++® 5.0 Product Release Bulletin (Rev. 3.0)8/30/2007
Lockbox Secure Technology2/14/2015
ClearSignal – Auto™3/3/2022
Software & Systems Requirements
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ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
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