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Features
- 8 channels of LNA, VGA, AAF, ADC, and digital RF decimator
- Low power:
- 150 mW per channel, TGC mode, 40 MSPS
- 62.5 mW per channel, CW mode - 10 mm × 10 mm, 144-ball CSP_BGA
- TGC channel input referred noise: 0.82 nV/√Hz, maximum gain
- Flexible power-down modes
- Fast recovery from low power standby mode: 2 μs
- Low noise preamplifier (LNA)
- Input referred noise:
0.78 nV/√Hz, gain = 21.6 dB - Programmable gain: 15.6 dB, 17.9 dB, or 21.6 dB
- 0.1 dB compression: 1000 mVP-P, 750 mVP-P, or 450 mVP-P
- Flexible active input impedance matching
- Variable gain amplifier (VGA)
- Attenuator range: 45 dB, linear in dB gain control
- Postamp gain (PGA): 21 dB, 24 dB, 27 dB, or 30 dB
- Antialiasing filter (AAF)
- Programmable second-order low-pass filter (LPF) from 8 MHz to 18 MHz or 13.5 MHz to 30 MHz and high-pass filter (HPF)
- Analog-to-digital converter (ADC)
- SNR: 75 dB, 14 bits up to 125 MSPS
- JESD204B Subclass 0 coded serial digital outputs
- See data sheet for additional features
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The AD9675 is designed for low cost, low power, small size, and ease of use for medical ultrasound. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA), a continuous wave (CW) harmonic rejection I/Q demodulator with programmable phase rotation, an antialiasing filter (AAF), an analog-to-digital converter (ADC), and a digital high-pass filter and RF decimation by 2 for data processing and bandwidth reduction.
Each channel features a maximum gain of up to 52 dB, a fully differential signal path, and an active input preamplifier termination. The channel is optimized for high dynamic performance and low power in applications where a small package size is critical.
The LNA has a single-ended to differential gain that is selectable through the serial port interface (SPI). Assuming a 15 MHz noise bandwidth (NBW) and a 21.6 dB LNA gain, the LNA input SNR is 94 dB. In CW Doppler mode, each LNA output drives an I/Q demodulator that has independently programmable phase rotation with 16 phase settings.
Power-down of individual channels is supported to increase battery life for portable applications. Standby mode allows quick power-up for power cycling. In CW Doppler operation, the VGA, AAF, and ADC are powered down. The ADC contains features to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudorandom patterns, and custom user-defined test patterns entered via the SPI.
APPLICATIONS
- Medical imaging/ultrasound
- Nondestructive testing (NDT)
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AD9675
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ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9675KBCZ |
144-Ball CSPBGA (10mm x 10mm x 1.4mm)
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- AD9675KBCZ
- Pin/Package Drawing
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144-Ball CSPBGA (10mm x 10mm x 1.4mm)
- Documentation
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HTML
Material Declaration
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HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
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SamacSys
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Part Models
Product Lifecycle
PCN
Mar 23, 2015
- 15_0033
AD9671/AD9675 Die Revision
AD9675KBCZ
PRODUCTION
Filter by Model
Part Models
Product Lifecycle
PCN
Mar 23, 2015
- 15_0033
AD9671/AD9675 Die Revision
Software & Part Ecosystem
| Parts | Product Life Cycle | Description | ||
|---|---|---|---|---|
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Clock Distribution Devices5 |
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RECOMMENDED FOR NEW DESIGNS |
800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
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|
RECOMMENDED FOR NEW DESIGNS |
1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
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|
RECOMMENDED FOR NEW DESIGNS |
1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
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|
RECOMMENDED FOR NEW DESIGNS |
1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer |
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RECOMMENDED FOR NEW DESIGNS |
Six LVPECL Outputs, SiGe Clock Fanout Buffer |
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Clock Generation Devices3 |
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RECOMMENDED FOR NEW DESIGNS |
1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs |
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RECOMMENDED FOR NEW DESIGNS |
1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
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RECOMMENDED FOR NEW DESIGNS |
1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
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Low Noise Op Amps (≤ 10nV/√Hz)2 |
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RECOMMENDED FOR NEW DESIGNS |
1 nV/√Hz, Low Power, Rail-to-Rail Output Amplifiers |
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RECOMMENDED FOR NEW DESIGNS |
1 nV/√Hz, Low Power Operational Amplifier |
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Single Channel A/D Converters1 |
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PRODUCTION |
18-Bit, 1 MSPS PulSAR ADC in MSOP/LFCSP |
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Single-Ended to Differential Amplifiers2 |
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PRODUCTION |
Low Distortion Differential ADC Driver |
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RECOMMENDED FOR NEW DESIGNS |
Low Power Differential ADC Driver |
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Can't find the software or driver you need?
Request a Driver/SoftwareEvaluation Kits 1
EVAL-AD9671
AD9671 Evaluation Board
Product Detail
The AD9671EBZ evaluation board enables testing and evaluation of the AD9671 octal ultrasound analog front end (AFE) device. The AD9671EBZ evaluation board offers eight Subminiature Version A (SMA) connector inputs for all eight channels. The AD9671EBZ evaluation board connects to the HSC-ADC-EVALEZ field programmable gate array (FPGA) data capture board, and enables data capture via a USB connection to a PC. SPIController software enables flexible configuration of the AD9671, and VisualAnalog® software offers a powerful data capture as well as signal analysis tools.
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