New Content (1)
Features and Benefits
JESD204B (Subclass 1) coded serial digital outputs
- Lane rates up to 15 Gbps
- 1.74 W total power at 1 GSPS
- 435 mW per ADC channel
- SFDR = TBD dBFS at 305 MHz (1.80 V p-p input range)
- SNR = TBD dBFS at 305 MHz (1.80 V p-p input range)
- Noise density = −151.5 dBFS/Hz (1.80 V p-p input range)
- 0.975 V, 1.8 V, and 2.5 V dc supply operation
- No missing codes
- Internal ADC voltage reference
- Analog input buffer
- On-chip dithering to improve small signal linearity
- Flexible differential input range
- 1.44 V p-p to 2.16 V p-p (1.80 V p-p nominal)
- 1.4 GHz analog input full power bandwidth
- Amplitude detect bits for efficient AGC implementation
- 4 integrated wideband digital processors
- 48-bit NCO, up to 4 cascaded half-band filters
- Differential clock input
- Integer clock divide by 1, 2, 4, or 8
- On-chip temperature diode
- Flexible JESD204B lane configurations
The AD9094 is a quad, 8-bit, 1 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 1.4 GHz. The AD9094 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.
The quad ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.
The analog inputs and clock signals are differential inputs. Each pair of ADC data outputs is internally connected to two DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator, NCO, and up to four half-band decimation filters.
In addition to the DDC blocks, the AD9094 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.
Users can configure each pair of intermediate frequency (IF) receiver outputs onto either one or two lanes of Subclass 1 JESD204B-based high speed serialized outputs, depending on the decimation ratio and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF±, SYNCINB±AB, and SYNCINB±CD input pins.
The AD9094 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using the 1.8 V capable, 3-wire SPI.
The AD9094 is available in a Pb-free, 72-lead LFCSP and is specified over the −40°C to +105°C junction temperature range. This product may be protected by one or more U.S. or international patents.
- Low power consumption per channel.
- JESD204B lane rate support up to 15 Gbps.
- Wide full power bandwidth supports IF sampling of signals up to 1.4 GHz.
- Buffered inputs ease filter design and implementation.
- Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers.
- Programmable fast overrange detection.
- On-chip temperature diode for system thermal management.
- Ultrawideband satellite receivers
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
The AD9094EVZ supports the AD9094, a quad, 14-bit, 500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed support communications applications capable of sampling analog signals of up to 1.4 GHz. This reference design provides all of the support circuitry required to operate the ADC in its various modes and configurations. It is designed to interface directly with the ADS7-V2EBZ data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device's hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The ACE software package is also compatible with this hardware, and allows the user to access the SPI programmable features of the AD9094.
Features & Benefits
- Full featured evaluation board for the AD9094
- SPI interface for setup and control
- Wide band Balun driven input
- External supply powered but may also use 12V-1A and 3.3V-3A supplies from FMC
- VisualAnalog® and SPI controller software interfaces
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
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The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.