- Integrated dual-channel RF front end
- 2-stage LNA and high power SPDT switch
- On-chip bias and matching
- Single supply operation
- High gain mode: 32 dB typical at 3.6 GHz
- Low gain mode: 16 dB typical at 3.6 GHz
- Low noise figure
- High gain mode: 1.45 dB typical at 3.6 GHz
- Low gain mode: 1.45 dB typical at 3.6 GHz
- High isolation
- RXOUT-CHA and RXOUT-CHB: 47 dB typical
- TERM-CHA and TERM-CHB: 52 dB typical
- Low insertion loss: 0.65 dB typical at 3.6 GHz
- High power handling at TCASE = 105°C
- Full lifetime
- LTE average power (9 dB PAR): 40 dBm
- Single event (<10 sec operation)
- LTE average power (9 dB PAR): 43 dBm
- Full lifetime
- High OIP3: 32 dBm typical
- Power-down mode and low gain mode for LNA
- Low supply current
- High gain mode: 86 mA typical at 5 V
- Low gain mode: 36 mA typical at 5 V
- Power-down mode: 12 mA typical at 5 V
- Positive logic control
- 6 mm × 6 mm, 40-lead LFCSP package
The ADRF5545A is a dual-channel, integrated radio frequency (RF), front-end multichip module designed for time division duplexing (TDD) applications that operates from 2.4 GHz to 4.2 GHz. The ADRF5545A is configured in dual channels with a cascading two-stage low noise amplifier (LNA) and a high power silicon single-pole, double-throw (SPDT) switch.
In high gain mode, the cascaded two-stage LNA and switch offer a low noise figure (NF) of 1.45 dB and a high gain of 32 dB at 3.6 GHz with an output third-order intercept point (OIP3) of 32 dBm (typical). In low gain mode, one stage of the two-stage LNA is in bypass, providing 16 dB of gain at a lower current of 36 mA. In power-down mode, the LNAs are turned off and the device draws 12 mA.
In transmit operation, when RF inputs are connected to a termination pin (TERM-ChA or TERM-ChB), the switch provides a low insertion loss of 0.65 dB and handles long-term evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 40 dBm for full lifetime operation and 43 dBm for single event (<10 sec) LNA protection operation.
The device comes in an RoHS compliant, compact, 6 mm × 6 mm, 40-lead LFCSP package.
- Wireless infrastructure
- TDD massive multiple input and multiple output and active antenna systems
- TDD-based communication systems
The ADRF5545A is a dual-channel integrated radio frequency (RF) front end ideally suited for time division duplexing (TDD) wireless infrastructure applications. The ADRF5545A is a multichip device that consists of a high power switch and a dual stage low noise amplifier on each channel.
This user guide describes the ADRF5545A-EVALZ evaluation board designed to easily evaluate the features and performance of the ADRF5545A. A photograph of the evaluation board is shown in Figure 1.
The ADRF5545A data sheet, available at www.analog.com, provides full specifications for the ADRF5545A. Consult the ADRF5545A data sheet in conjunction with this user guide when using the evaluation board.
- Full featured evaluation board for the ADRF5545A
- Easy connection to test equipment
- Matching network for 2.6 GHz and 3.6 GHz
- Thru line for calibration