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AD9548:  4/8路输入的网络时钟发生器/同步器

产品详情

产品状态:推荐用于新设计

AD9548可为包括同步光纤网络(SONET/SDH)在内的许多系统提供同步。它可以产生一个与高达四个差分或者八个单端外部输入基准之一同步的输出时钟。数字PLL能减少与外部基准有关的输入时间抖动或者相位噪声。即使当所有基准发生故障,AD9548仍能够利用数控环路和保持(holdover)电路连续产生有效的、干净的(低抖动)输出时钟。

AD9548可工作于-40°C至+85°C的工业温度范围。

应用
- 网络同步
- 基准时钟抖动清除
- GPS 1 每秒脉冲数同步
- SONET/SDH时钟,直到OC-192,包括前向纠错(FEC)
- Stratum 2保持(holdover),抖动清除,及相位瞬变控制
- Stratum 3/3E 基准时钟
- 无线基站,控制器
- 有线基础设施
- 数据通信

特点和优势

  • 在保持(holdover)模式下支持Stratum 2稳定性
  • 支持具有相位外建的基准转换
  • 支持无中断基准转换
  • 自动/手动保持(holdover)和基准转换
  • 4对基准输入引脚,每对皆可配置成单路差分输入或2路独立单端输入
  • 输入基准频率从1Hz至750MHz
  • 基准验证和频率监控(1ppm)
  • 可编程输入基准转换优先级
  • 欲了解更多特性,请参考数据手册。

AD9548功能框图

文档

快讯名称 内容类型 文件类型
AD9548: Quad/Octal Input Network Clock Generator/Synchronizer Data Sheet (Rev E, 12/2013) (pdf, 1870 kB) 产品数据手册 PDF
AN-1079: 确定AD9548系统时钟低环路带宽应用中的最大容许频率漂移速率  (pdf, 691 kB) 应用笔记 PDF
AN-1079: Determining the Maximum Tolerable Frequency Drift Rate of the AD9548 System Clock in Low Loop Bandwidth Applications  (pdf, 210 kB) 应用笔记 PDF
AN-1002: AD9548用作GPS可驯Stratum 2时钟  (pdf, 848 kB) 应用笔记 PDF
AN-1002: The AD9548 as a GPS Disciplined Stratum 2 Clock  (pdf, 157 kB) 应用笔记 PDF
AN-1064:了解AD9548的输入基准监控器  (pdf, 155 kB) 应用笔记 PDF
AN-1064: Understanding the Input Reference Monitors of the AD9548  (pdf, 155 kB) 应用笔记 PDF
AN-1061:存在随机抖动时鉴频鉴相器AD9548的特性  (pdf, 482 kB) 应用笔记 PDF
AN-1061: Behavior of the AD9548 Phase and Frequency Lock Detectors in the Presence of Random Jitter  (pdf, 470 kB) 应用笔记 PDF
AD9547/48: Profile Designer SW
The AD9548 is a quad/octal input network clock generator/synchronizer. This video covers the operation of the AD9548 Digital PLL Profile Designer, which is a key part of the evaluation software.
Videos HTML
AD9547/48: Evaluation Board SW Overview
The AD9548 is a quad/octal input network clock generator/synchronizer. This video is an overview of the AD9548 evaluation software.
Videos HTML
AD9547/48:评估板软件概述
AD9548是一款4路/8路输入网络时钟发生器/同步器。本视频概要说明AD9548评估软件。
Videos HTML
AD9548: GPS Clock Synchronization
Presented in this video is an overview of the AD9548 functionality and its evaluation board. Also shown is an actual application where the AD9548 is synchronized to a 1PPS reference supplied by a GPS antenna module.
Videos HTML
UG-639: Evaluating the AD9547 and AD9548 Digital PLL Clock Synthesizers  (pdf, 931 kB) 用户指导 PDF
Synchronizing NxN MIMO Basestations to an External Timing Reference
Understand how a high-performance clock generator, in conjunction with one or more integrated transceivers, simplifies overall design and reduces complexity and cost, while resulting in excellent system receive/transmit performance.
(RF DesignLine, 5/10/2010)
技术文章 HTML
RF 手册  (pdf, 988 kB)
RF IC 选型指南(12/2010)
概况 PDF
RAQs index 非常见问题解答 HTML
Why do I see reference spurs? 常见问题解答 HTML
Why is my phase noise shape changing when I change the PLL settings? 常见问题解答 HTML
Why doesn't the PLL make my reference input and the clock outputs line up? 常见问题解答 HTML
How do I optimize my PLL loop for the best phase noise and/or jitter? 常见问题解答 HTML
My loop is not locking. How do I debug this? 常见问题解答 HTML
How long does it take for the PLL to lock? 常见问题解答 HTML
Help! My PLL came unlocked over temperature. 常见问题解答 HTML
How do I choose between active and passive filter in PLL loop? 常见问题解答 HTML
Should I reference the passive filter to ground? or supply? 常见问题解答 HTML
How do the PLLs in the AD951x parts compare to other ADI PLLs? 常见问题解答 HTML
How does the clock clean-up function of the AD951x parts work? 常见问题解答 HTML
Why do I want to run a fast PFD frequency? 常见问题解答 HTML
Is it ok for me to connect the same power supply to both the charge pump and distribution power supply pins? 常见问题解答 HTML
Why can't I use a bandpass filter for my loop filter? 常见问题解答 HTML
Should I tie my loop filter to ground or PLL supply? 常见问题解答 HTML
The loop filter was working great until I changed the divide ratio in PLL. What happened? 常见问题解答 HTML
How do I use a VCO with a supply greater than 5V? 常见问题解答 HTML
What suppliers do you recommend for VCO/VCXOs? 常见问题解答 HTML
Do VCXOs have better phase noise and jitter performance than VCOs? 常见问题解答 HTML
How do I know which VCO will work best with the AD9510? 常见问题解答 HTML
Is there an advantage to running a higher VCO frequency than the output frequency? 常见问题解答 HTML
How do I determine if a VCO is good enough for my purpose? 常见问题解答 HTML
Is there any difference between the nature of an oscillator's phase noise and the phase noise from a clock chip? 常见问题解答 HTML
Do different divide ratios cause variations in jitter? 常见问题解答 HTML
I have a clocking scheme which requires several different division ratios simultaneously. I have a frequency plan, but I'm concerned about crosstalk. How much of a problem is this with your clock distribution chips? 常见问题解答 HTML
Do divide ratios change the propagation delay? 常见问题解答 HTML
I want to use the phase offset feature on the AD9510 dividers to generate two signals 90° out of phase. How accurate is the phase offset? 常见问题解答 HTML
On the AD951x clock ICs, does the phase offset (coarse delay) affect the jitter? 常见问题解答 HTML
Why doesn't the mini-divider support the divide ratio I want? 常见问题解答 HTML
I want to use the variable delay adjust, but the jitter is too high. What can I do? 常见问题解答 HTML
I changed the coarse phase adjust in the evaluation software, but nothing happened. What's going on? 常见问题解答 HTML
What is the difference between the coarse phase adjust and the fine delay adjust? 常见问题解答 HTML
What is the fine delay adjust which is available on certain LVDS/CMOS outputs? 常见问题解答 HTML
Does the fine delay adjust affect the jitter? 常见问题解答 HTML
Why is the fine delay adjust not available on all the outputs? 常见问题解答 HTML
Is there a way to cause Input/Output rising edges to be synchronous (zero delay) with the AD9510/11? 常见问题解答 HTML
Will the AD9510 work without a reference input signal? 常见问题解答 HTML
What are the best clock sources for a distribution-only design? 常见问题解答 HTML
I am not using the CLK1 input on the AD9510. Can I just leave it floating? 常见问题解答 HTML
How good does my input signal need to be? 常见问题解答 HTML
I turned off my reference but the Digital Lock Detect (DLD) still says I'm locked. 常见问题解答 HTML
Can I shift the threshold on clocks for single-ended inputs? 常见问题解答 HTML
The reference input is differential, but my reference is single-ended. Do I need to convert to differential to drive the AD9510? 常见问题解答 HTML
Will differential or single-ended inputs/outputs improve my jitter? 常见问题解答 HTML
Why should I use differential rather than single-ended? 常见问题解答 HTML
How do I feed a single-ended signal into a differential input? 常见问题解答 HTML
Why do you recommend AC coupling, rather than DC coupling, at the clock inputs? 常见问题解答 HTML
Are the ADI clock parts stand-alone clock sources or do I still have to buy a clock source to drive these parts? 常见问题解答 HTML
Which provides better performance - a clock source with sinewave output, or one with differential square wave outputs? 常见问题解答 HTML
On the AD9510, what is the relationship between clock output jitter and CLK1/CLK2 input slew rate? 常见问题解答 HTML
I'm trying to write to the part in single-byte mode, but I can't write anything. What am I doing wrong? 常见问题解答 HTML
Can I use the 951X clocks to drive a mixer (RF LO)? 常见问题解答 HTML
My applications are RF, not for clocking data converters. Can ADI's 951X ICs be used for RF applications? 常见问题解答 HTML
I have an input present at the clock input, but I'm not seeing an output? 常见问题解答 HTML
What happens to the AD9510/11 clock outputs if the Reference Input (REFIN) signal goes away? 常见问题解答 HTML
What clock frequency comes out of the AD9510 outputs when you first apply power to the device? 常见问题解答 HTML
Is it possible to impedance match a clock output if it is heavily loaded? (e.g. CL=100pF) 常见问题解答 HTML
I ran the AD9510 outputs at 1.4 GHz and they seem to work fine. Is there a problem running them at 1.4 GHz? 常见问题解答 HTML
What should I do with unused channels on the AD9510? 常见问题解答 HTML
Can I tri-state the AD9510 outputs? 常见问题解答 HTML
On the AD9510, how can I make sure that the duty cycle of output clocks stays within 40% to 60% duty cycle window? 常见问题解答 HTML
What is the effect of distributing harmonically related clocks (on chip or on board) in terms of jitter? 常见问题解答 HTML
Is there any reason to use a transformer on a differential clock output to obtain a "clean" single-ended clock output? 常见问题解答 HTML
What are some of the advantages/disadvantages of using LVPECL vs. LVDS outputs? 常见问题解答 HTML
Does the AD9510 support 2.5V PECL? 常见问题解答 HTML
How much bandwidth is required to process a PECL or LVDS output? 常见问题解答 HTML
If I use only one of the PECL differential outputs and the unused output is terminated in 50Ω, how will this affect the phase noise or jitter of the single-ended output? 常见问题解答 HTML
If I change the level of PECL output, does it affect the jitter? 常见问题解答 HTML
What is the best way to terminate LVPECL outputs to get lowest jitter? 常见问题解答 HTML
Is it okay to AC-couple PECL or LVDS outputs? 常见问题解答 HTML
What is the fan-out capability of the CMOS, LVDS, and LVPECL outputs? 常见问题解答 HTML
What is the proper termination (value and location) for outputs? 常见问题解答 HTML
Are outputs short-circuit protected? 常见问题解答 HTML
Are the CMOS drivers on the clock devices complementary? 常见问题解答 HTML
Some of the schematics in the AD951x data sheets show an LVPECL termination scheme which is different from the classic termination often seen (50 Ω to Vs - 2V, or the Thevenin equivalent thereof). How does this work, and how did you chose 200 Ω for the resistors? Can I use 100 ohms to improve the slew rate (or jitter)? 常见问题解答 HTML
I have pulled SYNCB low, but I still have output from a channel. Why? 常见问题解答 HTML
Why can I not get the same output amplitude or rise and fall times as stated in your datasheet? 常见问题解答 HTML
The AD9510 datasheet says to use an external pull-up resistor on the FUNCTION pin. Why do I need this and what range of resistors will work? 常见问题解答 HTML
May I use the AD9540 for spread spectrum clocking? 常见问题解答 HTML
Can I get two clock outputs from the AD9540? 常见问题解答 HTML
What's the advantage of a DDS-based clock generator? 常见问题解答 HTML
Why does the AD9540 require special filtering on its analog output. What are the requirements of this filter? 常见问题解答 HTML
I'm working with optical networks - SONET/SDH. Do ADI's clock chips support these applications? 常见问题解答 HTML
On my board, I can't get the same low jitter numbers that are shown in the datasheet. Am I doing something wrong? 常见问题解答 HTML
How do you determine the bandwidth over which phase noise is integrated to obtain jitter? 常见问题解答 HTML
Using the "ADC SNR method", what is the equivalent bandwidth for the jitter specification? 常见问题解答 HTML
How do harmonic spurs in the output spectrum affect jitter (random or deterministic)? 常见问题解答 HTML
When a jitter number is specified without an associated bandwidth, what bandwidth should be assumed? 常见问题解答 HTML
How do you specify jitter? 常见问题解答 HTML
How do I use the clock part for jitter clean-up? 常见问题解答 HTML
If jitter can be calculated from phase noise measurements, is it possible to calculate phase noise from jitter numbers? 常见问题解答 HTML
Does jitter vary with different clock frequencies? How about phase noise? 常见问题解答 HTML
I sure can't measure jitter with femtosecond resolution on my scope! How do you do it? How much confidence do you have in the jitter figures that you are quoting for these parts? 常见问题解答 HTML
Do you guarantee performance shown in ADIsimCLK? 常见问题解答 HTML
Who do I contact for technical support on ADIsimCLK? 常见问题解答 HTML
Should I use the minimum charge pump current settings in order to minimize power? 常见问题解答 HTML
Can I run CMOS outputs at 5V? 常见问题解答 HTML
Can I use different power supply voltages for the PECL output drivers? 常见问题解答 HTML
Is .01 uF sufficient for power supply pin bypass? 常见问题解答 HTML
My application has pretty tight power consumption requirements. I am very interested in the capabilities of the AD9510, but I don't need every feature. Is it possible to turn off the unused features and save power? 常见问题解答 HTML
Why don't you spec psrr and cmrr in the datasheet? 常见问题解答 HTML
How do I get two AD951x (with PLL) to synchronize to the same reference input edge? 常见问题解答 HTML
I really need >10 clock outputs. Can I use multiple chips together and still guarantee that all output clocks are synchronized to REFIN? 常见问题解答 HTML
How do I synchronize multiple clock devices? 常见问题解答 HTML
What happens if I run the part in an ambient environment which exceeds 85°C? 常见问题解答 HTML
How can I determine the die temperature of your device? 常见问题解答 HTML
My circuit board has both an analog GND and a digital GND. How should I connect the AD9510 pins labeled GND? 常见问题解答 HTML
What PCB layout recommendations do you have for the of the exposed paddle on the bottom side of the LFCSP package? 常见问题解答 HTML
术语表 专业词汇表 HTML

设计工具,模型,驱动及软件

快讯名称 内容类型 文件类型
AD9548 IBIS Models IBIS 模型 HTML

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AD9548 型号选项
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这里所列出的美国报价单仅供预算参考,指美元报价(规定订量的每片美元,美国离岸价),如有修改不再另行通知。由于地区关税、商业税、汇率及手续费原因,国际报价可能不同。对于特殊批量报价,请与您当地的ADI公司办事处或代理商联络。对于评估板和套件的报价是指一个单位价格。

AD9548 评估板
产品型号 描述 报价 RoHS 查看PCN/PDN 查看库存/
购买/样片
AD9548/PCBZ 产品状态: 联络ADI Evaluation Board $ 250.00 -

所示报价为单片价格。所列的美国报价单仅供预算参考,指美元报价(每片美国离岸价),如有修改,恕不另行通知。由于地区关税、商业税、汇率及手续费原因,国际报价可能不同。

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