Volume 33, Number 5, May, 1999
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Phase-locked loops for high-frequency receivers and transmitters-Part 2
The first part of this series of articles introduced the basic concepts of phase-locked loops (PLLs). The PLL architecture and principle of operation was described and accompanied by an example of where a PLL might be used in a communication system.
In this second part, we will focus on a detailed examination of two critical specifications associated with PLLs: phase noise and reference spurs. What causes them and how can they be minimized? The discussion will include measurement techniques and the effect of these errors on system performance. We will also consider output leakage current, with an example showing its significance in open-loop modulation schemes.
Noise in Oscillator Systems
Short-term stability, on the other hand, is concerned with variations that occur over a period of seconds or less. These variations can be random or periodic. A spectrum analyzer can be used to examine the short-term stability of a signal. Figure 1 shows a typical spectrum, with random and discrete frequency components causing a broad skirt and spurious peaks.
The discrete spurious components could be caused by known clock frequencies in the signal source, power line interference, and mixer products. The broadening caused by random noise fluctuation is due to phase noise. It can be the result of thermal noise, shot noise and/or flicker noise in active and passive devices.
Phase Noise in Voltage-Controlled Oscillators
wo represents an output signal of angular velocity, wo. Superimposed on this is an error signal represented by wm. To quantify this error, it is possible to take the rms value of the phase fluctuations and express them as Dq. This then is the phase error or jitter and may be express in rms picoseconds (ps rms) or rms degrees (q rms).
In many radio systems, an overall integrated phase error specification must be met. This overall phase error is made up of the PLL phase error, the modulator phase error and the phase error due to base band components. In GSM, for example, the total allowed is 5 q rms.
For Leeson's equation to be valid, the following must be true:
In theory, the noise power density is made up of equal magnitudes of AM (amplitude-modulated) and PM (phase-modulated) components. This would mean that the total noise power density is twice that given above. However, in practice, PM noise dominates at frequencies close to the carrier and AM noise dominates at frequencies somewhat distant from the carrier.
Leeson's equation only applies in the knee region between the break (f1) to the transition from the "1/f" (more generally 1/fgamma) flicker noise frequency to a frequency beyond which amplified white noise dominates (f2). This is shown in Figure 3 [gamma = 3]. f1 should be as low as possible; typically, it is less than 1 kHz, while f2 is in the region of a few MHz. High-performance oscillators require devices specially selected for low 1/f transition frequency. Some guidelines to minimizing the phase noise in VCO's are:
Closing The Loop
Figure 4 shows the main phase noise contributors in a PLL. The system transfer function may be described by the following equations.
For the discussion that follows, we will define SREF as the noise that appears on the reference input to the phase detector. It is dependent on the reference divider circuitry and the spectral purity of the main reference signal. SN is the noise due to the feedback divider appearing at the frequency input to the phase detector. SCP is the noise due to the phase detector (depending on its implementation). And SVCO is the phase noise of the VCO as described by equations developed earlier.
The overall phase noise performance at the output depends on the terms described above. All the effects at the output are added in an rms fashion to give the total noise of the system. Thus:
The noise terms at the PD inputs, SREF and SN, will be operated on in the same fashion as SREF and will be multiplied by the closed loop gain of the system.
At low frequencies, inside the loop bandwidth,
At high frequencies, outside the loop bandwidth,
The overall output noise contribution due to the phase detector noise, SCP, can be calculated by referencing SCP back to the input of the PFD. The equivalent noise at the PD input is SCP/Kd. This is then multiplied by the closed-loop gain:
Finally, the contribution of the VCO noise, SVCO, to the output phase noise is calculated in a similar manner. The forward gain this time is simply 1. Therefore its contribution to the output noise is:
G, the forward loop gain of the closed loop response, is usually a low pass function; it is very large at low frequencies and small at high frequencies. H is a constant, 1/N. The denominator of the above expression is therefore low pass, so SVCO is actually high-pass filtered by the closed loop.
A similar description of the noise contributors in a PLL/VCO can be found in Reference 1. Recall that the closed-loop response is a low-pass filter with a 3-dB cutoff frequency, Bw, denoted the loop bandwidth. For frequency offsets at the output less than Bw, the dominant terms in the output phase noise response are X and Y, the noise terms due to reference noise, N (counter noise), and charge pump noise. Keeping SN and SREF to a minimum, keeping Kd large and keeping N small will thus minimize the phase noise inside the loop bandwidth, Bw. Because N programs the output frequency, it is not generally available as a factor in noise reduction.
For frequency offsets much greater than Bw, the dominant noise term is that due to the VCO, SVCO. This is due to the high pass filtering of the VCO phase noise by the loop. A small value of Bw would be desirable as it would minimize the total integrated output noise (phase error). However a small Bw results in a slow transient response and increased contribution from the VCO phase noise inside the loop bandwidth. The loop bandwidth calculation therefore must trade off transient response and total output integrated phase noise.
To show the effect of closing the loop on a PLL, Figure 5 shows an overlay of the output of a free-running VCO and the output of a VCO as part of a PLL. Note that the in-band noise of the PLL has been attenuated compared to that of the free-running VCO.
Phase Noise Measurement
With the spectrum analyzer we can measure the one-sided spectral density of phase fluctuations per unit bandwidth. VCO phase noise is best described in the frequency domain where the spectral density is characterized by measuring the noise sidebands on either side of the output signal center frequency. Single-sideband phase noise power is specified in decibels relative to the carrier (dBc/Hz) at a given frequency offset from the carrier. The following equation describes this SSB phase noise (dBc/Hz).
The 10-MHz, 0-dBm reference oscillator, available on the spectrum analyzer's rear-panel connector, has excellent phase noise performance. The R divider, N divider, and the phase detector are part of ADF4112 frequency synthesizer. These dividers are programmed serially under the control of a PC. The frequency and phase noise performance are observed on the spectrum analyzer
Figure 8 illustrates a typical phase noise plot of a PLL synthesizer using an ADF4112 PLL with a Murata VCO, MQE520-1880. The frequency and phase noise were measured in a 5-kHz span. The reference frequency used was FREF = 200 kHz (R=50) and the output frequency was 1880 MHz (N=9400) . If this were an ideal-world PLL synthesizer, a single discrete tone would be displayed rising up above the spectrum analyzer's noise floor. What is displayed here is the tone, with the phase noise due to the loop components. The loop filter values were chosen to give a loop bandwidth of approximately 20 kHz. The flat part of the phase noise for frequency offsets less than the loop bandwidth is actually the phase noise as described by X2 and Y2 in the section "closing the loop" for cases where f is inside the loop bandwidth. It is specified at a 1-kHz offset. The value measured, the phase-noise power in a 1-Hz bandwidth, was -85.86 dBc/Hz. It is made up of the following:
When the PLL is in lock, the phase and frequency inputs to the PFD (fREF and fN) are essentially equal, and, in theory, one would expect that there to be no output from the PFD. However, this can create problems (to be discussed in part 3 of this series), so the PFD is designed such that, in the locked condition, the current pulses from the charge pump will typically be as shown in Figure 10.
Although these pulses have a very narrow width, the fact that they exist means that the dc voltage driving the VCO is modulated by a signal of frequency fREF. This produces reference spurs in the RF output occurring at offset frequencies that are integer multiples of fREF. A spectrum analyzer can be used to detect reference spurs. Simply increase the span to greater than twice the reference frequency. A typical plot is shown in Figure 11. In this case the reference frequency is 200 kHz and the diagram clearly shows reference spurs at ±200 kHz from the rf output of 1880 MHz. The level of these spurs is -90 dB. If the span were increased to more than four times the reference frequency, we would also see the spurs at (2´ fREF).
Charge Pump Leakage Current
A block diagram of open loop modulation is shown in Figure 12. The principle of operation is as follows: The loop is initially closed to lock the rf output, fOUT = N fREF. The modulating signal is turned on and at first the modulation signal is simply the dc mean of the modulation. The loop is then opened, by putting the CP output of the synthesizer into high-impedance mode, and the modulation data is fed to the Gaussian filter. The modulating voltage then appears at the VCO where it is multiplied by KV. When the data burst finishes, the loop is returned to the closed loop mode of operation.
As the VCO usually has a high sensitivity (typical figures are between 20 and 80 MHz/volt), any small voltage drift before the VCO will cause the output carrier frequency to drift. This voltage drift, and hence the system frequency drift, is directly dependent on the leakage current of the charge pump, CP, when in the high impedance state. This leakage will cause the loop capacitor to charge or discharge depending on the polarity of the leakage current. For example, a leakage current of 1 nA would cause the voltage on the loop capacitor (1000 pF for example) to charge or discharge by dV/dt=I/C (1 mV/ms in this case). This, in turn, would cause the VCO to drift. So, if the loop is open for 1 ms and the KV of the VCO is 50 MHz/Volt, the frequency drift caused by 1-nA leakage into a 1000-pF loop capacitor would be 50 kHz. In fact, the DECT bursts are generally shorter (0.5 ms), so the drift will be even less in practice for the loop capacitance and leakage current used in the example. However, it does serve to illustrate the importance of charge-pump leakage in this type of application.
Wideband noise in the LO can elevate the IF noise level and thus degrade the overall noise factor. For example, wideband phase noise at FLO + FIF will produce noise products at FIF. This directly impacts the receiver sensitivity. This wideband phase noise is primarily dependent on the VCO phase noise.
Close-in phase noise in the LO will also impact sensitivity. Obviously, any noise close to FLO will produce noise products close to FIF and impact sensitivity directly.
In the final part of this series, we will examine the building blocks that go to make up a PLL synthesizer. In addition, there will be a comparison between integer-N and fractional-N architectures for PLL.