AD9557:  Dual-Input Multiservice Line Card Adaptive Clock Translator

The AD9557 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9557 generates an output clock synchronized to one or two external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9557 continuously generates a low jitter output clock even when all reference inputs have failed.

The AD9557 operates over an industrial temperature range of −40°C to +85°C.

APPLICATIONS

• Network synchronization including synchronous Ethernet and SDH to OTN mapping / demapping
• Cleanup of reference clock jitter
• SONET/SDH clocks up to OC-192, including FEC
• Stratum 3 holdover, jitter cleanup, and phase transient control
• Wireless base station controllers
• Cable infrastructure
• Data communications