The AD9262 is a dual, 16-bit analog-to-digital converter (ADC) based on a continuous time sigma-delta (Σ-Δ) architecture that achieves -87 dB of dynamic range over a 10 MHz input bandwidth. The integrated features and characteristics unique to the continuous time Σ-Δ architecture significantly simplify its use and minimize the need for external components.
The AD9262 has a resistive input impedance that significantly relaxes the requirements of the driver amplifier. In addition, a 32× oversampled 5th-order continuous time loop filter significantly attenuates out of band signals and aliases, reducing the need for external filters at the input.
An external clock input or the integrated integer-N PLL provides the 640 MHz internal clock needed for the oversampled continuous time Σ-Δ modulator. On-chip decimation filters and sample rate converters reduce the modulator data rate from 640 MSPS to a user-defined output data rate between 30 MSPS to 160 MSPS, enabling a more efficient and direct interface.
The AD9262 incorporates an integrated dc correction and quadrature estimation block that corrects for gain and phase mismatch between the two channels. This functional block proves invaluable in complex signal processing applications such as direct conversion receivers.
The digital output data is presented in offset binary, Gray code, or twos complement format. A data clock output (DCO) is provided to ensure proper timing with the receiving logic. The AD9262 has the added feature of interleaving Channel A and Channel B data onto one 16-bit bus, simplifying on-board routing.
The ADC is available in three different bandwidth options of 2.5 MHz, 5 MHz, and 10 MHz, and operates on a 1.8 V analog supply and a 1.8 V to 3.3 V digital supply, consuming 600 mW. The AD9262 is available in a 64-lead LFCSP and is specified over the industrial temperature range (−40°C to +85°C).
|Title||Content Type||File Type|
|AD9262: 16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to 160 MSPS Dual Continuous Time Sigma-Delta ADC Data Sheet (Rev A, 02/2010) (pdf, 86 kB)||Data Sheets|
|AN-1236: Interfacing the ADL5382 Quadrature I/Q Demodulator to the AD9262 16-Bit Continuous Time Sigma-Delta ADC as an RF-to-Bits Solution (pdf, 109 kB)||Application Notes|
|AN-1142: Techniques for High Speed ADC PCB Layout (pdf, 392 kB)||Application Notes|
|AN-878: High Speed ADC SPI Control Software (pdf, 585 kB)||Application Notes|
|AN-282: Fundamentals of Sampled Data Systems (pdf, 2131 kB)||Application Notes|
|AN-807: Multicarrier WCDMA Feasibility (pdf, 969 kB)||Application Notes|
AN-808: Multicarrier CDMA2000 Feasibility
(pdf, 1535 kB)
The goal of this application note is to determine the feasibility of implementing a multicarrier CDMA2000 transceiver and what the major subsystem performances must be.
|AN-877: Interfacing to High Speed ADCs via SPI (pdf, 1594 kB)||Application Notes|
|AN-905: VisualAnalog Converter Evaluation Tool Version 1.0 User Manual (pdf, 2124 kB)||Application Notes|
|AN-835: Understanding High Speed ADC Testing and Evaluation (pdf, 985 kB)||Application Notes|
AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit (pdf, 452,449 bytes)
(pdf, 441 kB)
This application note describes the operation of a general-purpose, microcontroller-based Serial Port Interface (SPI) boot circuit.
AN-283: Sigma-Delta ADCs and DACs
(pdf, 1699 kB)
Overview of Sigma-Delta Concepts: Oversampling, Noise Shaping Using the Sigma-Delta Modulator, Digital Filtering and Decimation.
AD9262: Dual Continuous Time Sigma-Delta ADC
This video features the thought leaders (engineers and marketeers) involved with the creation of the AD9262. The AD9262 is a dual, 16-bit analog-to-digital converter (ADC) based on a continuous time sigma-delta architecture that achieves 86 dB of dynamic range over a 10 MHz input bandwidth.
|UG-051: Evaluating the AD9262, 16-Bit, Dual Continuous Time Sigma Delta ADC and Demonstrating Direct Conversion (pdf, 1200 kB)||User Guides|
|MS-2210: Designing Power Supplies for High Speed ADC (pdf, 327 kB)||Technical Articles|
Understanding Continuous-Time, Discrete-Time Sigma-Delta ADCs And Nyquist ADCs
Due to the high performance, efficiency, and ease of use of the CT-ΣΔ architecture, manufacturers of high-performance analog-to-digital converters (ADCs) are now bringing this converter architecture to market as a standard product.
(Electronic Design, February 20, 2009)
|AD926x Family 16-Bit, 10 MHz Bandwidth, Continuous-Time Sigma-Delta (CTSD) Analog-to-Digital Converters (pdf, 1406 kB)||Overview|
|Data Converter ICs Solutions Bulletin, Volume 10, Issue 7||Solutions Bulletins||HTML|
|RAQs index||Rarely Asked Questions||HTML|
|Glossary of EE Terms||Glossary||HTML|
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ADIsimADC is Analog Devices' Analog-to-Digital Behavioral Model that accurately models the typical performance characteristics of many of our High Speed Converters. The model faithfully reproduces the errors associated with both static and dynamic features such as AC linearity, clock jitter, and many other product specific anomalies.
|ADIsim Design/Simulation Tools||HTML|
|AD9262 IBIS Model||IBIS Models||HTML|
Recommended Driver Amplifiers for the AD9262
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