Abstract
This article explores a highly integrated commercial-off-the-shelf (COTS) software-defined radio (SDR) system-on-module (SOM) and evaluates its reconfigurability to minimize power consumption for mobile electronic warfare and communications applications, while maintaining essential receiver-only capabilities for spectral monitoring.
Introduction
Certain electronic warfare (EW) and communications applications require the deployment of mobile systems with lower power consumption for longer operating periods, and receiver-only capabilities for spectral monitoring. This article addresses these applications by evaluating the ADRV9009-ZU11EG, which combines two Analog Devices ADRV9009 transceivers and an AMD Zynq UltraScale+ MPSoC ZU11EG on a single printed circuit board (PCB) to create a highly integrated commercial-off-the-shelf (COTS) software-defined radio (SDR) system-on-module (SOM). Figure 1 shows an image of the SOM.
Each ADRV9009 transceiver has two transmit, two receive, and two observation receivers giving the SOM a total of four transmit channels, four receive channels, and four observation receiver channels. The SOM enables many different use cases–including, but not limited to, FR1 communications, scaling channel count for MIMO systems, and minimizing power consumption for deployment in power-constrained applications. Table 1 shows the SOM’s original four transmit, four receive configuration and power consumption compared to an intermediate two receive configuration, and the final low power two receive configuration and power consumption.
Table 1. SOM Configuration with Power Consumption
| Channel Configuration | Original | Intermediate | Low Power |
| Power Consumption (W) | 31.5 | 17.2 | 10 |
Test Setup
To evaluate the SOM, there are a few required pieces of hardware and software:
- ADRV9009-ZU11EG SOM
- ADRV2CRR-FMC
- PC running Windows or Linux
- EVAL-ADP-I2C-USB
- 12 V, 6-pin power supply
Figure 2 outlines the setup.
The ADRV2CRR-FMC is the carrier card that the SOM connects to. The EVAL-ADP-I2C-USB controller provides the ability to communicate with the SOM’s on-board ADM1266 to monitor voltage rails and program different voltage parameters, such as input thresholds. The computer allows the user to leverage a comprehensive suite of tools to evaluate the SOM including IIO Oscilloscope, Python libraries, and connection verification through Ethernet or UART. The SOM’s wiki page holds all the necessary information to evaluate the SOM. All testing and power measurements were completed at room temperature in a controlled lab environment. Further temperature evaluation would be required to validate power measurements for deployment in other environments.
Baseline Capability
The SOM operates from 75 MHz to 6 GHz and offers 200 MHz RF bandwidth in the receivers at 245.76 MSPS sample rate on the ADCs and up to 450 MHz RF bandwidth for the transmitters and observation receivers at 491.52 MSPS sample rate on the DACs. There are processing subsystem (PS) and programmable logic (PL) banks of DDR memory for the multiprocessor system-on-chip (MPSoC) and data handling, HMC7044B for clocking, and numerous communications interfaces. Figure 3 provides an overview of the SOM.
The clock chips support two main operating modes: the SOM’s default clock architecture leverages the on-board HMC7044B and the HMC7044B on the carrier card for multichip sync (MCS). MCS is a technique used to synchronize the on-board transceiver chips. This architecture is scalable based upon the number of clock chips cascaded. The other mode is clock distribution mode where the internal PLLs are bypassed. Some of the differences between these clock modes are discussed in this article, but for more information on the different HMC7044B operating modes, MCS capabilities of the SOM, and trade-offs for using either mode, visit the SOM wiki page. Figure 4 shows the default clock architecture.
In the default four receive, four transmit, zero observation receiver channel configuration at max sample rates and bandwidths, with no initialization calibrations, the SOM’s power consumption was measured to be 31.5 W. The on-board ADM1177 power management integrated circuit (PMIC) was utilized to measure system power consumption along with a Python script that averaged eight measurements from the PMIC to ensure any peaks or valleys would not skew the power data. See the wiki for the Python power averaging script.
A method used for verifying power consumption values included summing the power consumption of each active component on board and estimating the efficiency of the components in the power distribution network (PDN). With this approach, some of the most notable power consumption contributors were the ADRV9009 transceivers, HMC7044B and AD9542 clock distribution chips, and the MPSoC and supporting circuitry—these provided targets to reduce the power consumption. The PDN efficiencies were estimated to be approximately 74% for the RF supplies and 84% for the digital supplies based upon voltages, estimated current draw per rail, and regulator operating mode. For more details on the PDN, hardware implementation documentation, schematic, and other design files, visit the SOM’s wiki page.
For comparison purposes, basic RF performance was evaluated on a receiver channel. For RF measurements, a signal generator was configured to sweep the ADRV9009’s full operating frequency range at –20 dBm power level input to a single receiver channel, which pushes the input tone close to the ADC full-scale input power. The in-band spurious-free dynamic range (SFDR) was captured by calculating the difference between the fundamental tone and the highest level spur within the desired spectrum. The average SFDR was calculated to be 78.5 dBc. This average was calculated with the linear dynamic range values captured before being converted to decibels with respect to the carrier.
Modifications to Reduce Power Consumption
To minimize power consumption, a combination of hardware and software changes must be realized. For basic software changes, IIO enabled tools such as ADI’s IIO Oscilloscope tool gives users the ability to reconfigure SDR parameters with a GUI. Some features of the tool include turning on/off channels, enabling/disabling initialization or tracking calibrations, reconfiguring frequencies/bandwidths, and monitoring capabilities such as plotting FFTs or reading/writing registers of SPI connected devices. Python can also be leveraged to perform the same changes, but the tool was used for ease of implementation. For more in-depth changes, new software builds must be compiled and loaded in hardware description language (HDL). Configuring new software builds in HDL gives the user the ability to fully disable functions rather than simply turning them off.
The targeted use case for the SOM was a receive only, 2-channel minimum configuration, but the details outlined in this article can be utilized to estimate the power consumption of many different use cases by comparing the baseline SOM measurements and intermediate results per change. The initial receiver only use-case configuration consisted of four receive channels at 200 MHz bandwidth with the ADCs running at 245.76 MSPS, tracking calibrations enabled, initialization calibrations disabled, observation receivers disabled, and the transmitters disabled with their JESD links fully removed in HDL. The system power consumption was observed to be 23.4 W. A comparison between the baseline measurement and this configuration shows that the ADRV9009 transmitters (with JESD enabled) consume approximately 8 W, or 2 W per transmitter.
To see how much power could be saved with IIO Oscilloscope, one of the on-board ADRV9009 transceivers was powered down by using the power down function on a set of receivers, leaving two operating receivers. The unused clock outputs of the HMC7044B identified in the schematic were also disabled. The combination of changes outlined decreased the power consumption of the system to 21.9 W. In the next HDL build, one of the ADRV9009 transceivers was fully disabled by eliminating its JESD links and reconfigured the other transceiver with a lower sample rate of 122.88 MSPS and 100 MHz instantaneous bandwidth (IBW). In this configuration, the power consumption of the SOM measures 17.2 W.
To reduce power consumption further, noncritical power contributors were identified for minimum SOM operation. Minimum SOM operation assumes the MPSoC would be utilized for data processing. The SOM has two sets of DDR chips on board: PS DDR and PL DDR. PS DDR is used in most cases and is crucial for operatingthe SOM. PLDDR is typically accessed when a significant amount of PS DDR is occupied by other on-board tasks. With the minimized channel configuration and lower sample rate, the PL DDR chips would not be required, so they were disabled in HDL. Other peripherals such as USB 3.0, DisplayPort, and serial gigabit media-independent interface (SGMII) Ethernet functions were disabled. The AD9542 clock chip was also disabled. Additionally, the input voltage of the SOM was reduced to 5 V by performing a few pin configuration changes to the LTM4636 power IC and by reprogramming the over/undervoltage thresholds in ADI Power Studio with the EVAL-ADP-I2C-USB. Lowering the input voltage to certain regulators can help mitigate additional power loss. By performing these changes, the power consumption of the SOM was measured to be 12.8 W.
For applications with stricter power constraints, significant hardware modification is required. The power supplies were placed into pulse skipping or Burst Mode® with pin configuration changes, which boosts the overall efficiency of the supplies at lower current draw. The MPSoC side PL_DDR rails were shorted to ground, the PL DDR chips and power supplies were physically removed, as well as the AD9542, the disabled ADRV9009, unused crystals, and the unused HMC7044B low voltage positive emitter-coupled logic (LVPECL) clock pull ups to ensure there was no leakage current being supplied to the disabled components. The input frequency of the HMC7044B was reduced to 245.76 MHz and configured for clock distribution mode to bypass the internal PLLs, and the MPSoC’s Arm® core frequencies were reduced from 1.3 GHz to 300 MHz. With these changes, the power consumption of the SOM was measured to be 10 W. Figure 5 provides a block diagram representation of the SOM after implementing the modifications previously outlined.
Table 2 estimates the power consumption of the highest power consumption contributors in the SOM from the original configuration, the intermediate case, and after the additional hardware and software changes for this use case.
Table 2. ADRV9009-ZU11EG SOM Power Contributions
| Device | Original Power | Intermediate Power | Low Power (W) |
| XCZU11EG | 5.1 | 5.1 | 3 |
| ADRV9009 | 12.8 | 4.8 | 4.2 |
| HMC7044B | 2.6 | 2.6 | 1.5 |
| DDR4 | 2 | 2 | 1 |
| AD9542 | 1 | 1 | 0 |
| Other | 8 | 1.7 | 0.3 |
| Total | 31.5 | 17.2 | 10 |
The other row corresponds to all other power in the system, including other active components, passive power dissipation, and supply efficiency. Once these modifications were performed, the same test setup/methodology was used to gather in-band RF data. The average SFDR was calculated to be 83.1 dBc, which is a few dB higher than the default SOM. Despite having slightly increased SFDR performance, the trade-offs for the low power SOM configuration should be considered. With the transmitter JESD links disabled in HDL, the low power SOM configuration outlined has no ability to transmit data. The removal of the PL DDR chips, and HDL removal of certain peripherals eliminates the SOM’s ability to offload the data at the configured sample rate. Finally, the change in the clock architecture of the SOM to the clock distribution has significant implications. Figure 6 shows the new clocking architecture.
The carrier HMC7044B supplies a 245.76 MHz reference input and the on-board HMC7044B acts as a buffer that divides the input reference frequency. The on-board clock chip cannot synchronize on-board transceivers in this mode. This implies the low power SOM configuration can only have the single ADRV9009 transceiver and without on-board channel count scalability.
Table 3 summarizes the differences between the original configuration, intermediate configuration, and the low power configuration.
Table 3. Features Difference Between Default and Low Power SOM
| Original | Intermediate | Low Power | |
| Transmitters | Yes | No | No |
| Data Offload | Yes, through multiple interfaces | Yes, through multiple interfaces | No, all processing on board |
| On-Board Channel Count Scalable | Yes | Yes | No |
As shown in Table 3, the low power configuration of the SOM does not have the ability to transmit due to the ADRV9009 transmitter being disabled in HDL. All data processing must be completed on board due to the high speed data offload interfaces being disabled and the PL DDR chips being removed.
Conclusion
The ADRV9009-ZU11EG’s software and hardware reconfigurability enables deployment in power-constrained applications. ADI’s IIO-based libraries or tools such as IIO Oscilloscope can be leveraged to evaluate the power consumption of the SOM with a user-friendly interface and minimal effort. Optimizing the PDN efficiency on SOM by lowering the input voltage threshold and changing the operating modes of the on-board power ICs can increase the overall efficiency. Reconfiguring the HDL to reduce sample rates and operating bandwidths, and disabling unused features or peripherals, reduces power further without the need for hardware modifications. For applications where power consumption must be absolutely minimized, a combination of the changes outlined above with significant hardware modifications can be made to realize greatly reduced power consumption, at the cost of most of the additional features inherent to the SOM such as on-board channel count scalability.
Reference
ADRV9009-ZU11EG RF System-on-Module. Analog Devices, Inc.
