ADF5612
ADF5612
新規設計に推奨Microwave Wideband Synthesizer with Integrated VCO
- 製品モデル
- 3
- 1Ku当たりの価格
- 最低価格:$26.00
Viewing:
製品の詳細
- RFOUT output frequency range: 7300MHz to 8500MHz
- PDIV_OUT and NDIV_OUT frequency range: 57MHz to 8500MHz
- Fractional-N synthesizer and Integer N synthesizer modes
- Typical PFD spurious: <−105dBc
- Integrated RMS jitter at 1kHz to 100MHz integration bandwidth: <40fs
- Normalized inband phase noise floor FOM
- Integer mode: −232dBc/Hz
- Fractional mode: −229dBc/Hz
- Maintains frequency lock over −40°C to +105°C (lock and leave)
- Low open-loop VCO phase noise
- −115dBc/Hz typical at 100kHz offset (RFOUT at 7.3GHz)
- RFOUT power (typical): 6dBm
- Programmable divide by 1, 2, 4, 8, 16, 32, 64, or 128 output
- Programmable output power level
- Typical power dissipation: 1W
- 48-terminal, 7 mm × 7 mm LGA package: 49 mm2
The ADF5612 allows implementation of fractional-N or Integer N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference source. The wideband microwave voltage controlled oscillator (VCO) design permits frequency operation from 7300MHz to 8500MHz at a single RF output. A series of frequency dividers with a differential frequency output allows operation from 57MHz to 8500MHz. Analog and digital power supplies for the PLL circuitry range from 3.15V to 3.45V, and the VCO supplies are between 4.75V and 5.25V.
The ADF5612 has an integrated VCO with a fundamental frequency of 3650MHz to 7300MHz. These frequencies are internally doubled and routed to the RFOUT pin. An additional differential output allows the doubled VCO frequency to be divided by 1, 2, 4, 8, 16, 32, 64, or 128, allowing the user to generate RF output frequencies as low as 57MHz. A simple 3-wire or 4-wire serial port interface (SPI) provides control of all on-chip registers. To conserve power, this divider block can be disabled when not needed through the SPI. Likewise, the output power for both the single-ended output and the differential output are programmable.
The integrated phase detector and Δ-Σ modulator, capable of operating at up to 100MHz, permit wide loop bandwidths and fast frequency tuning with a typical spurious level of −105dBc.
With a VCO open-loop phase noise at 100kHz offset of −115dBc/Hz at 7.3GHz RFOUT. The ADF5612 is equipped to minimize blocker effects and to improve receiver sensitivity and transmitter spectral purity. The low phase noise floor eliminates any contribution to modulator and mixer noise floor in transmitter applications.
APPLICATIONS
- Military and defense
- Test equipment
- Clock generation
- Wireless infrastructure
- Satellite and very small aperture terminals (VSATs)
- Microwave radios
ドキュメント
データシート 1
ユーザ・ガイド 1
製品モデル | ピン/パッケージ図 | 資料 | CADシンボル、フットプリント、および3Dモデル |
---|---|---|---|
ADF5612CCCZ | LGA/CASON/CH ARRY SO NO LD | ||
ADF5612CCCZ-RL7 | LGA/CASON/CH ARRY SO NO LD | ||
EV-ADF5612SD1Z | NON-PHYSICAL PROD:NRE,ETC. |
これは最新改訂バージョンのデータシートです。
ツールおよびシミュレーション
ADIsimPLL™
ADIsimPLLは、アナログ・デバイセズの新しい高性能PLL製品の迅速で信頼性の高い評価を可能にします。これは、現在利用できる最も包括的なPLLシンセサイザ設計およびシミュレーション・ツールです。実施されるシミュレーションには、PLL性能に影響を与える重要な非線形効果がすべて含まれます。ADIsimPLLは、設計プロセスから1回以上の反復作業を削除し、設計から市場投入までの時間を短縮します。
ツールを開くIBISモデル 1
評価用キット
最新のディスカッション
ADF5612に関するディスカッションはまだありません。意見を投稿しますか?
EngineerZone®でディスカッションを始める