Features and Benefits
- RF bandwidth: 25 MHz to 3000 MHz
- 3.3 V supply
- Maximum phase detector rate: 100 MHz
- Ultralow phase noise
- −110 dBc/Hz in band (typical), fO at 2000 MHz
- Fractional figure of merit (FOM): −226 dBc/Hz
- 24-bit step size, 3 Hz typical resolution
- Exact frequency mode with 0 Hz frequency error
- Fast frequency hopping
- 40-lead, 6 mm × 6 mm LFCSP package: 36 mm2
The HMC832A is a 3.3 V, high performance, wideband, fractional-N, phase-locked loop (PLL) that features an integrated voltage controlled oscillator (VCO) with a fundamental frequency of 1500 MHz to 3000 MHz and an integrated VCO output divider (divide by 1, 2, 4, 6, … 62) that enables the HMC832A to generate continuous frequencies from 25 MHz to 3000 MHz. The integrated phase detector (PD) and Σ-Δ modulator, capable of operating at up to 100 MHz, permit wider loop bandwidths and faster frequency tuning with excellent spectral performance.
Industry leading phase noise and spurious performance, across all frequencies, enable the HMC832A to minimize blocker effects, and to improve receiver sensitivity and transmitter spectral purity. A low noise floor (−160 dBc/Hz) eliminates any contribution to modulator/mixer noise floor in transmitter applications.
The HMC832A is footprint compatible to the market leading HMC830 PLL with an integrated VCO. It features 3.3 V supply and an innovative programmable performance technology that enables the HMC832A to tailor current consumption and corresponding noise floor performance to individual applications by selecting either a low current consumption mode or a high performance mode for an improved noise floor performance.
Additional features of the HMC832A include 12 dB of RF output gain control in 1 dB steps; an output mute function to automatically mute the output during frequency changes when the device is not locked; selectable output return loss; programmable differential or single-ended outputs, with the ability to select either output in single-ended mode; and a Σ-Δ modulator exact frequency mode that enables users to generate output frequencies with 0 Hz frequency error; and a register configurable 3.3 V or 1.8 V serial port interface (SPI).
- Cellular infrastructure
- Microwave radios
- WiMax, WiFi
- Communications test equipment
- CATV equipment
- DDS replacement
- Tunable reference sources for spurious-free performance
Product Lifecycle Production
At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
Tools & Simulations
For those developers dealing with integer boundary spurs from Analog’s PLL synthesizers, the best solution is ADIsimFrequencyPlanner. The frequency planner quickly analyzes the PFD frequency for a user’s output requirements and then optimizes the frequency of each output to identify the highest contributing integer boundary spur performance.
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Support & Discussions
Sample & Buy
The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.