Features and Benefits
- RF 2 × 2 transceiver with integrated 12-bit DACs and ADCs
- Transmit band: 46.875 MHz to 6.0 GHz
- Receive band: 70 MHz to 6.0 GHz
- Dual receivers: 6 differential or 12 single-ended inputs
- Superior receiver sensitivity with a NF of 2 dB at 800 MHz LO
- Receive gain control
- Real-time monitor and control signals for manual gain
- Independent AGC
- Dual transmitters: 4 differential outputs
- Highly linear broadband transmitter
- Transmit EVM: −40 dB (typical) at 800 MHz
- Transmit noise: −157 dBm/Hz (typical)
- Transmit monitor: 66 dB dynamic range (typical) with 1 dB accuracy
- Integrated fractional-N synthesizers
- 2.4 Hz typical LO frequency step size
- Multichip synchronization
- CMOS/LVDS digital interface
Commercial Space Features
- Wafer diffusion lot traceability
- Radiation lot acceptance testing: TID
The AD9361S-CSL is a high performance, highly integrated, RF agile transceiver designed for use in 3G and 4G applications. Its programmability and wideband capability make it ideal for a broad range of transceiver applications. The device combines an RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor. The AD9361S-CSL receiver LO operates from 70 MHz to 6.0 GHz and the transmitter LO operates from 46.875 MHz to 6.0 GHz range, covering most licensed and unlicensed bands. Channel bandwidths from less than 200 kHz to 56 MHz are supported.
The two independent direct conversion receivers have state-of-the-art noise figure and linearity. Each receive subsystem includes independent automatic gain control (AGC), dc offset correction, quadrature correction, and digital filtering, thereby eliminating the need for these functions in the digital baseband. The AD9361S-CSL also has flexible manual gain modes that can be externally controlled.
Two high dynamic range analog-to-digital converters (ADCs) per channel digitize the received inphase (I) and quadrature (Q) signals and pass them through configurable decimation filters and 128-tap finite impulse response (FIR) filters to produce a 12-bit output signal at the appropriate sample rate.
The transmitters use a direct conversion architecture that achieves high modulation accuracy with ultralow noise. This transmitter design produces a best-in-class transmit error vector magnitude (EVM) of ≤−40 dB, allowing significant system margin for the external power amplifier (PA) selection. The on-board transmit power monitor can be used as a power detector, enabling highly accurate transmit power measurements.
The fully integrated phase-locked loops (PLLs) provide low power fractional-N frequency synthesis for all receive and transmit channels. Channel isolation, demanded by frequency division duplex (FDD) systems, is integrated into the design. All voltage controlled oscillator (VCO) and loop filter components are integrated. The AD9361S-CSL is packaged in a 10 mm × 10 mm, 144-ball chip scale package ball grid array (CSP_BGA).
- Low Earth orbit (LEO) satellites
- Point to point communication systems
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
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