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HMC832A

LAST TIME BUY

Fractional-N PLL with Integrated VCO 25 MHz to 3000 MHz

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Overview

  • RF bandwidth: 25 MHz to 3000 MHz
  • 3.3 V supply
  • Maximum phase detector rate: 100 MHz
  • Ultralow phase noise
    • −110 dBc/Hz in band (typical), fO at 2000 MHz
  • Fractional figure of merit (FOM): −226 dBc/Hz
  • 24-bit step size, 3 Hz typical resolution
  • Exact frequency mode with 0 Hz frequency error
  • Fast frequency hopping
  • 40-lead, 6 mm × 6 mm LFCSP package: 36 mm2

The HMC832A is a 3.3 V, high performance, wideband, fractional-N, phase-locked loop (PLL) that features an integrated voltage controlled oscillator (VCO) with a fundamental frequency of 1500 MHz to 3000 MHz and an integrated VCO output divider (divide by 1, 2, 4, 6, … 62) that enables the HMC832A to generate continuous frequencies from 25 MHz to 3000 MHz. The integrated phase detector (PD) and Σ-Δ modulator, capable of operating at up to 100 MHz, permit wider loop bandwidths and faster frequency tuning with excellent spectral performance.

Industry leading phase noise and spurious performance, across all frequencies, enable the HMC832A to minimize blocker effects, and to improve receiver sensitivity and transmitter spectral purity. A low noise floor (−160 dBc/Hz) eliminates any contribution to modulator/mixer noise floor in transmitter applications.

The HMC832A is footprint compatible to the market leading HMC830 PLL with an integrated VCO. It features 3.3 V supply and an innovative programmable performance technology that enables the HMC832A to tailor current consumption and corresponding noise floor performance to individual applications by selecting either a low current consumption mode or a high performance mode for an improved noise floor performance.

Additional features of the HMC832A include 12 dB of RF output gain control in 1 dB steps; an output mute function to automatically mute the output during frequency changes when the device is not locked; selectable output return loss; programmable differential or single-ended outputs, with the ability to select either output in single-ended mode; and a Σ-Δ modulator exact frequency mode that enables users to generate output frequencies with 0 Hz frequency error; and a register configurable 3.3 V or 1.8 V serial port interface (SPI).

Applications

  • Cellular infrastructure
  • Microwave radios
  • WiMax, WiFi
  • Communications test equipment
  • CATV equipment
  • DDS replacement
  • Military
  • Tunable reference sources for spurious-free performance

HMC832A
Fractional-N PLL with Integrated VCO 25 MHz to 3000 MHz
HMC832A Functional Block Diagram HMC832A Pin Configuration
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Software Resources

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Hardware Ecosystem

Parts Product Life Cycle Description
Comparators 1
LTC6957 Low Phase Noise, Dual Output Buffer/Driver/Logic Converter
Phase-Locked Loop (PLL) Synthesizers 1
HMC1031 LAST TIME BUY 0.1 MHz to 500 MHz Clock Generator with Integer N PLL
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Tools & Simulations

ADIsimFrequency Planner Tool

For those developers dealing with integer boundary spurs from Analog’s PLL synthesizers, the best solution is ADIsimFrequencyPlanner. The frequency planner quickly analyzes the PFD frequency for a user’s output requirements and then optimizes the frequency of each output to identify the highest contributing integer boundary spur performance.

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Evaluation Kits

EVAL-HMC832A
HMC832A Evaluation Board
HMC832 Evaluation Board HMC832 Evaluation Board - Top View HMC832 Evaluation Board - Bottom View

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